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| flexray communication freescale.com controllers mfr4200 data sheet mfr4200 rev. 0 8/2005
mfr4200 data sheet mfr4200 rev. 0 8/2005 mfr4200 data sheet, rev. 0 4 freescale semiconductor to provide the most up-to-date info rmation, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify that you have the latest information available, refer to http://www.freescale.com the following revision history ta ble summarizes chang es contained in this document. for your convenience, the page number designators ha ve been linked to the appropriate location. revision history date revision level description page number(s) 08/2005 0 initial release. n/a mfr4200 data sheet, rev. 0 freescale semiconductor 5 introduction device overview mfr4200 flexray communication controller dual output voltage regulator (vreg3v3v2) clocks and reset generator oscillator (oscv2) electrical characteristics package information printed circuit board layout recommendations mfr4200 protocol implementation document index of registers mfr4200 data sheet, rev. 0 6 freescale semiconductor mfr4200 data sheet, rev. 0 freescale semiconductor 7 contents section number title page chapter 1 introduction 1.1 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 additional reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 part number coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 2 device overview 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1.2 implementation details and constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1.5 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.1.6 part id assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.1 system pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.2 pin functions and signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.3 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 2.2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3 system clock description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.2 recommended pullup/down resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.3 host controller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.4 external output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4.5 mfr4200 connection to flexray network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.6 power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 mfr4200 data sheet, rev. 0 8 freescale semiconductor section number title page chapter 3 mfr4200 flexray comm unication controller 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.1 mfr4200 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.2 mfr4200 implementation parameters and constraints . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.2 register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 3.2.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3 message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.3.1 message buffer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 41 3.3.2 message buffer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.3.3 message buffer slot status vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.3.4 message id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.3.5 nmvector fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.3.6 data[0:31] ? data fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 3.4 message buffer control, configuratio n, status and filtering re gister set . . . . . . . . . . . . . . . . . 150 3.4.1 message buffer control, configuration and status re gister . . . . . . . . . . . . . . . . . . . . . 150 3.4.2 message buffer filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.4.3 receive fifo filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.5 message buffer handling and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 60 3.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5.2 buffer map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5.3 active message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 61 3.5.4 buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 3.5.5 buffer reconfiguration in the normal state of oper ation . . . . . . . . . . . . . . . . . . . . . . . 172 3.5.6 message buffer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.6 receive fifo function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.7 host controller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.7.1 mfr4200 asynchronous memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.7.2 mfr4200 hcs12 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.8 external 4/10 mhz output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.9 communication controller states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.9.1 hard reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.9.2 configuration state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 3.9.3 diagnosis stop state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 3.9.4 normal active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.9.5 normal passive state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.10 debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 3.10.1 debug port overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 3.10.2 debug port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.10.3 debug port function timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 mfr4200 data sheet, rev. 0 freescale semiconductor 9 section number title page chapter 4 dual output voltage regulator (vreg3v3v2) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.2.1 v ddr , v ssr ? regulator power input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.2.2 v dda , v ssa ? regulator reference supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.2.3 v dd , v ss ? regulator output1 (core logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.2.4 v ddosc , v ssosc ? regulator output2 (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.2.5 v regen ? optional regulator enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.3.1 reg ? regulator core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.3.2 full-performance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 0 4.3.3 por ? power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.3.4 lvr ? low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.3.5 ctrl ? regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.4 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.4.1 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.4.2 low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 chapter 5 clocks and reset generator 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.2.1 mfr4200 pins relevant to the crg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.2.2 reset generation and clkout control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 chapter 6 oscillator (oscv2) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.2.1 v ddosc and v ssosc ? osc operating voltage, osc ground . . . . . . . . . . . . . . . . . . 217 6.2.2 extal and xtal ? clock/crystal source pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 mfr4200 data sheet, rev. 0 10 freescale semiconductor section number title page appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 a.2 voltage regulator (vreg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 a.2.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 a.2.2 chip power-up and voltage drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 a.2.3 output loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 a.3 reset and oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 a.3.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 a.3.2 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 a.4 ami interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 a.5 hcs12 interface timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 appendix b package information b.1 64-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 appendix c printed circuit board layout recommendations appendix c mfr4200 protocol implementation document c.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 c.1.1 purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 c.1.2 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 c.1.3 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 c.2 overall protocol state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 c.3 coding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 c.3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 c.3.2 nrz coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 c.3.3 nrz decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mfr4200 data sheet, rev. 0 freescale semiconductor 11 section number title page c.3.4 signal integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 c.4 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 c.5 media access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 c.6 frame and symbol processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 c.7 wakeup, startup, and reintegration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 c.7.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 c.7.2 cluster wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 c.7.3 communication startup and reintegra tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 c.8 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 c.8.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 c.8.2 time representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 c.8.3 synchronization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 52 c.8.4 clock startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 c.8.5 time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 c.8.6 correction term calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 c.8.7 clock correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 c.8.8 sync frame configuration rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 c.9 controller host interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 c.10 device specific power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 c.11 bus guardian schedule monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 c.12 system parameters and configuration c onstraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 c.12.1 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 c.12.2 configuration constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 appendix d index of registers mfr4200 data sheet, rev. 0 12 freescale semiconductor section number title page mfr4200 data sheet, rev. 0 freescale semiconductor 13 list of figures figure number title page figure 1-1. order part number coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 2-1. mfr4200 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 2-2. pin assignments for mfr4200 in 64-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 2-3. pierce oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 2-4. external clock connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 2-5. clock connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 2-6. clkout generation during power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 2-7. clkout generation during low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 2-8. clkout generation during extern al hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 2-9. example: connecting a fl exray optical/electrical phy to th e mfr4200. . . . . . . . . . . 50 figure 2-10. example: connecting an rs485 phy to the mfr4200. . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 3-1. key to register diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 3-2. module version register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 3-3. module version register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 3-4. magic number register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 3-5. module configuration re gister 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 3-6. module configuration re gister 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 3-7. host interface pins drive strength register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 3-8. physical layer pins drive stre ngth register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3-9. host interface pins pullup/down enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3-10. host interface pins pullup/down control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 3-11. physical layer pins pullup/down enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 3-12. physical layer pins pullup/down control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 3-13. voltage regulator status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 3-14. bit duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 3-15. delay compensation channel a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 3-16. delay compensation channel b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 3-17. cluster drift damping register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 3-18. maximum sync frames register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 figure 3-19. nominal macrotick length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 3-20. microticks per cycle low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 3-21. microticks per cycle high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mfr4200 data sheet, rev. 0 14 freescale semiconductor figure number title page figure 3-22. static slot length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 3-23. number of static slots register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 3-24. static payload length register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 3-25. minislot length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 3-26. minislot action point offset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 3-27. static slot action point offset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 3-28. latest dynamic transmission st art register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 3-29. maximum payload length dynamic register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 3-30. symbol window configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 3-31. network idle time configurati on register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 3-32. cycle length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 3-33. maximum cycle length deviation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 3-34. external offset correction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 3-35. external rate correc tion register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 3-36. external correction control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 3-37. maximum offset correction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 3-38. maximum rate correction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 3-39. coldstart maximum register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 3-40. transmit start sequence length re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 3-41. network management vector le ngth register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 3-42. sync frame register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 3-43. sync frame header register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 3-44. bus guardian tick register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 3-45. delay counter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 3-46. debug port control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 3-47. start of offset correction cycl e time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 3-48. idle detection length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 3-49. symbol window control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 0 figure 3-50. wakeup mechanism control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 3-51. wakeup symbol tx idle register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 figure 3-52. wakeup symbol tx low register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 3-53. listen timeout with noise lengt h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 3-54. protocol state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 3-55. current cycle counter value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 3-56. current macrotick counter value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 mfr4200 data sheet, rev. 0 freescale semiconductor 15 figure number title page figure 3-57. offset correction value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 3-58. rate correction value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 3-59. global network management v ector n register, n = [0:5] . . . . . . . . . . . . . . . . . . . . . . . 96 figure 3-60. symbol window status channel a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 3-61. symbol window status channel b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 3-62. bus guardian status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 3-63. startup interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 3-64. maximum odd cycles without clock correction fatal register . . . . . . . . . . . . . . . . . 101 figure 3-65. maximum odd cycles without clock correction passive register . . . . . . . . . . . . . . . 101 figure 3-66. channel status error counter n register, n = [0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 3-67. interrupt enable register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 3-68. slot status selection n register, n = [0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 3-69. slot status counter n register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 3-70. slot status counter condition n register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 3-71. slot status counter incrementation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 3-72. slot status counter interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 3-73. receive buffer interr upt vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 3-74. transmit buffer interrupt vect or register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 3-75. chi error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 3-76. clock correction failed counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 3-77. error handling level register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 3-78. interrupt status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 3-79. startup interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 3-80. slot status n register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 3-81. odd sync frame id n register, n = [0:15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 3-82. even sync frame id n register , n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 3-83. odd measurement channel a n register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 3-84. odd measurement channel b n register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 3-85. even measurement channel a n register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 3-86. even measurement channel b n register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 3-87. even measurement counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 3-88. odd measurement counter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 3-89. fifo size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 3-90. message buffer control, configuration and status n register , n = [0:58] . . . . . . . . . . 126 figure 3-91. active transmit buffer frame id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 mfr4200 data sheet, rev. 0 16 freescale semiconductor figure number title page figure 3-92. active transmit buffer cycle counter and payload length register . . . . . . . . . . . . . . 127 figure 3-93. active transmit buffer header crc register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 3-94. active transmit buffer data n register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 3-95. active transmit buffer message buffer slot status vector register . . . . . . . . . . . . . . 128 figure 3-96. active receive buffer frame id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 3-97. active receive buffer cycle counter and pa yload length register . . . . . . . . . . . . . . . 129 figure 3-98. active receive buffer header crc register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 3-99. active receive buffer data n register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 3-100. active receive buffer mess age buffer slot status vector register . . . . . . . . . . . . . . . 131 figure 3-101. active fifo buffer frame id re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 3-102. active fifo buffer cycle counter and payload length register . . . . . . . . . . . . . . . . . 132 figure 3-103. active fifo buffer header crc register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 3-104. active fifo buffer data n re gister, n = [0:15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 3-105. active fifo buffer message buffer slot status vector register . . . . . . . . . . . . . . . . . 133 figure 3-106. sync frame acceptance filter value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 3-107. sync frame acceptance filter mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 3-108. sync frame rejection filter regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 35 figure 3-109. cycle counter filter n register, n = [0:58] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 3-110. fifo acceptance filter message id value regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 3-111. fifo acceptance filter messag e id mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 3-112. fifo acceptance/rejection filt er channel register . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 3-113. fifo rejection filter frame id value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 3-114. fifo rejection filter frame id mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 3-115. timer interrupt configuration register 0 cycle set . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 3-116. timer interrupt configuratio n register 0 macrotick o ffset . . . . . . . . . . . . . . . . . . . . . 140 figure 3-117. timer interrupt configuration register 1 cycle set . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 3-118. timer interrupt configuration re gister 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 3-119. transmit message buffer slot status vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 3-120. receive and receive fifo me ssage buffer slot status vector. . . . . . . . . . . . . . . . . . . 147 figure 3-121. bufcsnr of a receive message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 3-122. bufcsnr of a transmit message single bu ffer for the dynamic segm ent. . . . . . . . . 150 figure 3-123. bufcsnr of a host part transm it message buffer of a double tx buffer for the dynamic segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 3-124. bufcsnr of a host part transm it message buffer of a double tx buffer for the static segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 mfr4200 data sheet, rev. 0 freescale semiconductor 17 figure number title page figure 3-125. bufcsnr of a single transm it message buffer for the static segment . . . . . . . . . . . 151 figure 3-126. bufcsnr of a cc part transmit message buffer of a double tx buffer for dynamic and static segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 3-127. bufcsnr of fifo buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 3-128. ccfnr, transmit and receive message buffer filter registers . . . . . . . . . . . . . . . . . . 158 figure 3-129. ccfnr, cc part buffer of a double transmit message buffe r filter registers. . . . . . 158 figure 3-130. ccfnr, fifo buffer filter regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 figure 3-131. buffer control, configuration, stat us/filtering register set for transmit/receive buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 3-132. buffer control, confi guration, status/filtering register set for receive fifo buffers 163 figure 3-133. buffer busy bit timing for a transmit message buffer . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 3-134. example of a buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 70 figure 3-135. transition scheme between differ ent buffer types depending on operational mode of cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 3-136. operations during a frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 3-137. operations with a single transmit message buffer during an event type of transmission for a static segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 3-138. double transmit message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 3-139. doubled buffer data collection with state driven transmit operation . . . . . . . . . . . . 184 figure 3-140. doubled buffer data collection with event driven transmit operation . . . . . . . . . . . . 185 figure 3-141. fifo status (empty, not empty, overrun) ? example of fifo with three message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 figure 3-142. connecting mfr4200 to mpc5xx using the ami (example) . . . . . . . . . . . . . . . . . . . 190 figure 3-143. connecting mfr4200 to mac71xx using the ami (example) . . . . . . . . . . . . . . . . . . 191 figure 3-144. connecting mfr4200 to ds p56f83x (hawk) using the ami (example) . . . . . . . . . . 191 figure 3-145. flexray cc to hcs12 device connect ion with hcs12 ebi paged mode support. . . 193 figure 3-146. flexray cc to hcs12 device conn ection with hcs12 ebi unpaged mode support 194 figure 3-147. hcs12 interface address d ecoding and internal cs signal gene ration . . . . . . . . . . . . 195 figure 3-148. timing diagram of cc state transition fr om configuration state to normal state . . . 200 figure 3-149. start of communication cycle and start of offset correction func tions timing . . . . . 204 figure 3-150. timing for debug functions with three extal or cc_clk clock cycles of high state (logic ?1?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 3-151. slot start in static segment function timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 4-1. vreg3v3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 figure 5-1. power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 5-2. low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 5-3. external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 mfr4200 data sheet, rev. 0 18 freescale semiconductor figure number title page figure a-1. voltage regulator ? chip power-up and volt age drops (not scaled) . . . . . . . . . . . . . 230 figure a-2. ami interface read and write timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure a-3. ami interface write-after-read transactions timing diagram . . . . . . . . . . . . . . . . . . 234 figure a-4. ami interface read-after-write transactions timing diagram . . . . . . . . . . . . . . . . . . 234 figure a-5. hcs12 interface read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 figure b-1. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 1) . . . . . . . . . . . . . . . . 239 figure b-2. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 2) . . . . . . . . . . . . . . . . 240 figure b-3. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 3) . . . . . . . . . . . . . . . . 241 figure c-1. recommended pcb layout (64-pin lqfp) fo r standard pierce oscillator mode . . . . 244 figure c-1. protocol operation control (poc) - 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 figure c-2. protocol operation control (poc) - 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 figure c-3. poc ? normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 48 figure c-4. poc ? passive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 mfr4200 data sheet, rev. 0 freescale semiconductor 19 list of tables table number title page table 1-1. acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 1-2. notational conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2-1. interface selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 2-2. clockout selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 2-3. bus driver type selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 2-4. voltage regulator vddr connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 2-5. device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 2-6. assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 2-7. pin functions and signa l properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 2-8. mfr4200 power and ground connecti on summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 2-9. recommended pullup/down resistor values for if_sel[0:1] and clk_s[0:1] inputs . . 46 table 3-1. register map summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 3-2. bus driver type selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 3-3. encoding of debug port cont rol fields cntrl[7:4] and cntrl[3:0] . . . . . . . . . . . . . . 88 table 3-4. cc state coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 3-5. mapping between receive message buffer payload bytes and gnmvnr registers . . . . 96 table 3-6. channel configuration for ssccnr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 3-7. error handling level coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 3-8. mapping between sssnr and ssnr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 3-9. fifo size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 3-10. fifo channel filtering configura tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 table 3-11. receive message buffer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 3-12. receive fifo message buffer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 3-13. transmit message buffer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 3-14. mapping between buffer layout and active re ceive/transmit/fifo message buffers. 143 table 3-15. channel filtering configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 3-16. cc buffer fields acce ssibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 3-17. double transmit message buffer da ta collection with state driven transmit operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 3-18. double transmit message buffer da ta collection with event driven transmit operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 3-19. flexray cc mcu interface confi guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 3-20. ami interface signals and pins de scription. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 mfr4200 data sheet, rev. 0 20 freescale semiconductor table number title page table 3-21. hcs12 interface signal a nd pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 3-22. clkout frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 97 table 3-23. debug port functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 4-1. vreg3v3v2 ? signal properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 4-2. vreg3v3v2 ? reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 5-1. mfr4200 pins relevant to the crg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table a-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table a-2. esd and latch-up test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 table a-3. esd and latch-up protection char acteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table a-4. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table a-5. thermal package simulation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table a-6. 5v i/o characteristics (v dd5 = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table a-7. 3.3v i/o characteristics (vdd5 = 3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table a-8. supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table a-9. voltage regulator - operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table a-10. voltage regulator recommended capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table a-11. startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table a-12. oscillator characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table a-13. ami interface ac switching characteristics over the operating range . . . . . . . . . . . . 235 table a-14. hcs12 interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table c-1. suggested external component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 mfr4200 data sheet, rev. 0 freescale semiconductor 21 chapter 1 introduction this data sheet provides information on a system that includes the mfr4200 flexray communication controller module. 1.1 audience this data sheet is intended for appl ication and system hardware devel opers who wish to develop products for the flexray mfr4200. it is assumed that the read er understands flexray prot ocol functionality and microcontroller system design. 1.2 additional reading for additional reading that provides background to, or supplements, the information in this manual: appendix c, ?mfr4200 protocol implementation document ? for more information about the flexray protocol, refer to the following document: ? flexray communications syst em protocol specification v1.1, flexray consortium, 2004. for more information about philips bus guardian and bus driver devices, refer to the following documents: ? flexray electrical physic al layer specification, v1. 5, flexray consortium, 2004, ? flexray bus guardian preliminary functiona l specification, v1.9, flexra y consortium, june 2004. for more information about rs485 transceivers: ? about the max3078 transceiver (idle state coded as ?1?) http://pdfserv.maxim-ic.c om/en/ds/max3070e-max3079e.pdf ? about the max3485 transceiver (idle state coded as ?0?) http://pdfserv.maxim-ic.c om/en/ds/max3483-max3491.pdf for more information about the power pc interf ace, refer to the fre escale products section at www.freescale.com . for more information about m9hcs12 family devices and m9hcs12 pr ogramming, refer to the freescale products section at www.freescale.com . introduction mfr4200 data sheet, rev. 0 22 freescale semiconductor 1.3 terminology table 1-1. acronyms and abbreviations term meaning ami asynchronous memory interface bg bus guardian cc communication controller (an alternative term for the mfr4200) ceil function ceil(x) returns the nearest integer greater than or equal to x cycle length in t the actual length of a cycle in t for the idea l controller ( 0 ppm) ebi external bus interface fss frame start sequence host the flexray cc host mcu lsb less/least significant bit mcu microcontroller msb more/most significant bit mt macrotick t microtick nit network idle time phy physical interface ps flexray communications syst em protocol specification pwd protocol working document rx reception tcu time control unit tx transmission tdma time division multiplex access table 1-2. notational conventions active-high names of signals that are active-high are sh own in upper case text, without a ?#? symbol at the end. active-high signals are asserted (active) when they are high and negated when they are low. active-low a ?#? symbol at the end of a signal name indicates that the signal is active-low. an active-low signal is asserted (active) when it is at the logic low level and is negated when it is at the logic high level. asserted a signal that is asserted is in its active logic st ate. an active-low signal changes from high to low when asserted; an active-high signal changes from low to high when asserted. negated a signal that is negated is in its inactive logic state. an active-low signal changes from low tohigh when negated; an active-high signal chan ges fromhigh to low when negated. set to set a bit means to establish logic level one on the bit. clear to clear a bit means to establish logic level zero on the bit. part number coding mfr4200 data sheet, rev. 0 freescale semiconductor 23 1.4 part number coding figure 1-1. order part number coding 0x0f the prefix ?0x? denotes a hexadecimal number. 0b0011 the prefix ?0x? denotes a binary number. x in certain contexts, such as a signal encoding, this indicates ?don?t care?. for example, if a field is binary encoded 0bx001, the state of th e first bit is ?don?t care?. == used in equations, this symbol signifies comparison. table 1-2. notational conventions (continued) p fr 4200 m pb 40 speed option temperature option device title controller family qualification package option m = qualified part ae = 64-pin lead free / halide free lqfp 40 = 40 mhz pb = 64-pin lqfp m = -40 o c to +125 o c p = engineering sample introduction mfr4200 data sheet, rev. 0 24 freescale semiconductor introduction mfr4200 data sheet, rev. 0 freescale semiconductor 25 chapter 2 device overview 2.1 introduction the flexray communication controller mfr4200 impleme nts the flexray protocol in accordance with appendix c, ?mfr4200 protocol implementation document ?. this appendix refers to flexray communications system protocol specification v1.1 for most protoc ol mechanisms, and complements the protocol specifi cation where necessary. the controller host interface (chi) of the flexra y communication controller mfr4200 is implemented in accordance with chapter 3, ?mfr4200 flexray communication controller ?. 2.1.1 features the following list of features is not comprehensive, but is a selection of the most important features. detailed descriptions of the protocol and th e chi features are provided in the following. chapter 3, ?mfr4200 flexray communication controller ? appendix c, ?mfr4200 protocol implementation document ? the most important features are: bit rate up to a maximum of 10 mbit/sec on each of two channels. 59 message buffers, each with a payload of up to 32 bytes of data. flexray frames with up to 254 payl oad data bytes. padding is used for flexray payload data that exceeds the 32-byte data size boundary. one configurable receive fifo. each message buffer configurable as a receive m essage buffer, or as a transmit message buffer (single or double), or as pa rt of the receive fifo. two receive shadow message buffers available to each channel. message buffer configurable with state or event semantics. flexible error signaling mechanism providing eight configurable count ers, slot status indicators and interrupts. internal measured time difference values used fo r clock synchronization can be read via the chi. the status of up to four slots can be observe d independently of the communication controller receive buffers. the host accesses all messa ge buffers by means of three acti ve message buffers (active transmit message buffer, active message receive buffer, and active receive fifo buffer) in the chi. configurable message filtering based on frame id, cycle counter, and channel, for transmit and receive message buffers. configurable message filtering b ased on frame id, channel, and m essage id, for the receive fifo. duration of the communication cy cle configurable in microticks. device overview mfr4200 data sheet, rev. 0 26 freescale semiconductor 2.1.2 implementation details and constraints the mfr4200 provides two hardwa re selectable host interfaces: ? hcs12 interface, for direct connection to freescale?s hcs12 family of microcontrollers. the hcs12 interface clock signal used to synchroni ze data transfer can run at a maximum rate of 8 mhz. ? asynchronous memory interface (ami), for asynchronous connection to microcontrollers. internal 40 mhz quartz oscillator. internal voltage regulator for th e digital logic and the oscillator. hardware selectable clock output to driv e external host devices: disabled/4/10/40 mhz. maskable interrupt sources availa ble over one interrupt output line. glueless electrical physical layer interface comp atible with dedicated fl exray physical layer. industry standard rs485 physical layer device can be used with additional glue logic. two pins have multiplexed strobe functions. note refer to chapter 3, ?mfr4200 flexray communication controller ? for more implementation details and constraints. 2.1.3 modes of operation note this section depicts only the mfr420 0 device modes, not the flexray protocol operating modes of the mfr4200 flexray module. refer to chapter 3, ?mfr4200 flexray communication controller for more information on the flexray module operating modes. only one user mode is available on the mfr4200 ? normal operating mode. in normal operating mode, the select ions described below are possible. 2.1.3.1 interface selection the external interface is selected by m eans of the if_sel[0:1] pins, as shown in table 2-1 . table 2-1. interface selection pin interface if_sel0 if_sel1 00reserved 0 1 hcs12 synchronous interface 1 0 asynchronous memory interface 11reserved introduction mfr4200 data sheet, rev. 0 freescale semiconductor 27 note as the if_sel[0:1] signals share pins with physical laye r interface signals, the interface type must be selected using either pullu p or pulldown resistors. if_sel[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. refer to chapter 5, ?clocks and reset generator ? for more information. 2.1.3.2 clockout selection the clk_s[0:1] pins select the clkout pin output clock frequency or disable the output clock. note as clk_s[0:1] signals share pins with physical layer interface signals, the clkout function must be selected using either pullup or pulldown resistors. clk_s[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. refer to chapter 5, ?clocks and reset generator for more information. 2.1.3.3 bus driver type selection the scm[0:1] bits of the mcr0 register (see chapter 3, ?mfr4200 flexra y communication controller ) select the bus driver type. table 2-2. clockout selection pin clkout function clk_s0 clk_s1 0 0 4 mhz output 1 0 10 mhz output 0 1 40 mhz output 1 1 disabled (clkout output is ?0?) table 2-3. bus driver type selection driver type scm1 scm0 rs485 (idle state coded as ?0?) 1 1 refer to section 1.2, ?additional reading ? for more information on rs485. 00 optical/electrical phy 0 1 reserved 1 0 rs485 (idle state coded as ?1?) 1 11 device overview mfr4200 data sheet, rev. 0 28 freescale semiconductor note it is not possible to mix in a cluster or per channel: different rs485; rs485 and optical/electrical phy. 2.1.3.4 internal vreg enable/disable selection 2.1.4 block diagram figure 2-1 shows a block diagram of the mfr4200 device. table 2-4. voltage regulator vddr connection vddr description supplied with v dd5 1 1 refer to section a.1.7, ?operating conditions ? for the v dd5 internal voltage regulator enabled tied to ground internal voltage regulator disabled introduction mfr4200 data sheet, rev. 0 freescale semiconductor 29 figure 2-1. mfr4200 block diagram voltage regulator receiver channel a receiver channel b transmitter channel a transmitter channel b tcu external clock generator debug strobe oscillator clock and reset generation module host interface asynchronous memory interface hcs12 interface arm/dbg1/clk_s0 bgt/dbg2/if_sel0 mt/clk_s1 txen2#/ txe2_485# txd_bg1/txd1_485/if_sel1 bge2 rxd_bg2/rxd2_485 test supply pins bge1 txd_bg2/txd2_485 txen1#/ txe1_485# rxd_bg1/rxd1_485 d1/pad14 d0/pad15 d8/pad7 d7/pad8 d6/pad9 d5/pad10 d4/pad11 d3/pad12 d2/pad13 d14/pad1 d13/pad2 d12/pad3 d11/pad4 d10/pad5 d9/pad6 d15/pad0 vddx[1..4] vssx[1..4] acs5 a9/acs2 a7/acs0 a6/xaddr14 acs4 oe#/acs3 a8/acs1 a5/xaddr15 a4/xaddr16 a2/xaddr18 a1/xaddr19 a3/xaddr17 vssr vdd2_5 vddr vss2_5 vssr vdd2_5 vddr vss2_5 vddosc vssosc extal/cc_clk vddosc xtal vssosc reset# eclk_cc int_cc# ce#/lstrb we#/rw_cc# clkout/tm0 internal logic i/o driver oscillator vreg input vdda vssa vssa vdda vreg input analog clkout device overview mfr4200 data sheet, rev. 0 30 freescale semiconductor 2.1.5 memory map table 2-5 shows the device memory map of the mfr4200 after a hard reset. the flexray block defines the mfr4200 address memory map. refer to chapter 3, ?mfr4200 flexray communication controller for the detailed register map. table 2-5. device memory map address (hex) module size (bytes) 0x000?0x018 general control registers 26 0x01a?0x01e acceptance filter registers 6 0x024?0x04a general control registers 40 0x04c?0x082 slot status registers 56 0x084?0x0fe general control registers 124 0x100?0x126 active receive fifo buffer 40 0x128?0x13e reserved, read-only location 24 0x140?0x166 active receive message buffer 40 0x168?0x17e reserved, read-only location 24 0x180?0x1a6 active transmit message buffer 40 0x1a8?0x1fe reserved, read-only location 88 0x200?0x2fe buffer control, config uration and status registers, cycle counter filters registers 256 0x300?0x31e reserved, read-only location 32 0x320?0x3fe general status registers 224 signal descriptions mfr4200 data sheet, rev. 0 freescale semiconductor 31 2.1.6 part id assignments the part id is located in two 16-bit register s, mvr0 and mvr1, at addresses 0x002 and 0x098 (see chapter 3, ?mfr4200 flexray communication controller ). this read-only value is a unique part id for each revision of the chip. table 2-6 shows the assigned part id number. 2.2 signal descriptions this section describes the signals th at connect off-chip. it includes a pinout diagram, a table of signal properties, and a detailed discussion of each signal. 2.2.1 system pinout the mfr4200 is available in a 64-pin low profile quad flat package (lqfp). most pins perform two or more functions, as described in section 2.2.2, ?pin functions and signal properties ?. figure 2-2 shows the pin assignments. table 2-6. assigned part id numbers device mask set number part id 1 1 the coding is as follows (see also the mvr0 and mvr1 register descriptions in chapter 3, ?mfr4200 flexray communication controller ): mvr0: bit 15-12: major release of the flexray block in the mfr4200 device bit 11-08: minor release of the flexray block in the mfr4200 device bit 07-00: device part id1 mvr1: bit 15-08: device part id2. bit 07-04: major release of the mfr4200 device. bit 03-00: minor release of the mfr4200 device. mvr0 mvr1 mfr4200 0l60x 0x9042 0x0000 mfr4200 1l60x 0x9042 0x0001 device overview mfr4200 data sheet, rev. 0 32 freescale semiconductor figure 2-2. pin assignments for mfr4200 in 64-pin lqfp 2.2.2 pin functions and signal properties table 2-7 provides a summary of all pin func tions and signal properties shown in figure 2-2 . 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mt/clk_s1 2 arm/dbg1 1 /clk_s0 2 bge2 txd_bg2/txd2_485 txen2#txe2_485# rxd_bg2/rxd2_485 bge1 txd_bg1/txd1_485/if_sel1 2 d1/pad14 d0/pad15 vssx2 vddx2 txen1#/txe1_485# vddx4 acs5 rxd_bg1/rxd1_485 test d9/pad6 d10/pad5 d11/pad4 d12/pad3 d13/pad2 d14/pad1 vddx1 vssx1 d15/pad0 a1/xaddr19 a2/xaddr18 a3/xaddr17 a4/xaddr16 a5/xaddr15 reset# vssa vdda d2/pad13 eclk_cc vssx3 vddx3 d3/pad12 d4/pad11 d5/pad10 d6/pad9 vdd2_5 vss2_5 d7/pad8 d8/pad7 clkout int_cc# bgt/dbg2 1 /if_sel0 2 vssx4 we#/rw_cc ce#/lstrb acs4 oe#/acs3 vddosc xtal extal/cc_clk vssosc a9/acs2 a8/acs1 vddr vssr a7/acs0 a6/xaddr14 notes: 1 one of the following internal signals can be output through the dbg1 or dbg2 pin: pcs, sss, ragfb, mss, dssb, sfb, rcfb, scc, ragfa, mts, soc, dssa, sfa, rcfa. (see ta b l e 3 - 3 and ta b l e 3 - 2 3 .) 2 clk_s[1:0] and if_sel[1:0] are inputs during t he internal reset sequence, and are latched by the internal reset signal level. signal descriptions mfr4200 data sheet, rev. 0 freescale semiconductor 33 table 2-7. pin functions and signal properties pin n pin 1 function1 pin 1 function2 pin 1 function3 powered by in/ out pin type 2,3 re set functional description host interface pins 11 a1 xaddr19 - vddx i pc - ami address bus / hcs12 expanded address lines. a1= lsb of the ami address bus. 12 a2 xaddr18 - vddx i pc - ami address bus / hcs12 expanded address lines. 13 a3 xaddr17 - vddx i pc - ami address bus / hcs12 expanded address lines. 14 a4 xaddr16 - vddx i pc - ami address bus / hcs12 expanded address lines. 15 a5 xaddr15 - vddx i pc - ami address bus / hcs12 expanded address lines. 17 a6 xaddr14 - vddx i pc - ami address bus / hcs12 expanded address lines. xaddr14 = lsb of the hcs12 expanded address lines 18 a7 acs0 - vddx i pc - ami address bu s / hcs12 address select inputs. 21 a8 acs1 - vddx i pc - ami address bu s / hcs12 address select inputs. 22 a9 acs2 - vddx i pc - ami address bu s / hcs12 address select inputs. 27 oe# 4 acs3 - vddx i pc - ami read output enable signal / hcs12 address select input. 28 acs4 - - vddx i pc - hcs12 address select inputs. 34 acs5 - - vddx i pc - hcs12 address select inputs. msb of the address select inputs. 10 d15 pad0 - vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. pad0 is the lsb of the hcs12 address/data bus. 7 d14 pad1 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 6 d13 pad2 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 5 d12 pad3 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 4 d11 pad4 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 3 d10 pad5 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 2 d9 pad6 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. device overview mfr4200 data sheet, rev. 0 34 freescale semiconductor 62 d8 pad7 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 61 d7 pad8 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 58 d6 pad9 - vddx i/o z/dc/pc z ami data bu s / hcs12 multiplexed address/data bus. 57 d5 pad10 - vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. 56 d4 pad11 - vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. 55 d3 pad12 - vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. 51 d2 pad13 - vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. 40 d1 pad14 - vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. 39 d0 pad15 - vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. d0 is the lsb of the ami data bus 29 ce# lstrb - vddx i pc - ami chip select signal / hcs12 low-byte strobe signal 30 we# rw_cc# - vddx i pc - ami write enable signal/ hcs12 read/write select signal 52 eclk_cc - - vddx i pc - hcs12 clock input physical layer interface 32 bgt dbg2 if_sel0 vddx i/o dc/pd - bus guardian tick / debug strobe point signal 2/host interface selection 0 48 mt clk_s1 - vddx i/o dc/pd - bus guardian macrotick/controller clock output select signal 1 47 arm dbg1 clk_s0 vddx i/o dc/pd - bus guardian arm signal / debug strobe point signal1/controller clock output select signal 0 33 rxd_bg1 rxd2_485 - vddx i pc - phy data receiver input / rs485 data receiver input 43 rxd_bg2 rxd2_485 - vddx i pc - phy data receiver input / rs485 data receiver input 36 txen1# txe1_485# - vddx o dc 1 transmit enable for phy / transmit enable for rs485 44 txen2# txe2_485# - vddx o dc 1 transmit enable for phy / transmit enable for rs485 table 2-7. pin functions and signal properties (continued) pin n pin 1 function1 pin 1 function2 pin 1 function3 powered by in/ out pin type 2,3 re set functional description signal descriptions mfr4200 data sheet, rev. 0 freescale semiconductor 35 41 txd_bg1 txd1_485 if_sel1 vddx i/o dc/pd - phy data transmitter output / rs485 data transmitter output / host interface selection 1 45 txd_bg2 txd2_485 - vddx o dc 0 phy data transmitter output / rs485 data transmitter output 42 bgen1 - - vddx i pc - bus guardian enable monitor input 46 bgen2 - - vddx i pc - bus guardian enable monitor input clock signals 63 clkout - - vddx i/o dc - controller clock output selectable as disabled or 4/10/40 mhz others 16 reset# - - vddx i - - hardware reset input 64 int_cc# - - vddx o od/dc 1 controller interrupt output 1 test - - vddx i - - must be tied to logic low in application. oscillator 24 extal cc_clk - vddosc i - - crystal driver / external clock pin 25 xtal - - i - - crystal driver pin supply/bypass filter pins 8 vddx1 - - - - - - supply voltage, i/o 37 vddx2 - - - - - - supply voltage, i/o 54 vddx3 - - - - - - supply voltage, i/o 35 vddx4 - - - - - - supply voltage, i/o 9 vssx1 - - - - - - supply voltage ground, i/o 38 vssx2 - - - - - - supply voltage ground, i/o 53 vssx3 - - - - - - supply voltage ground, i/o 31 vssx4 - - - - - - supply voltage ground, i/o 20 vddr - - - - - - supply voltage, supply to pin drivers and internal voltage regulator 19 vssr - - - - - - supply voltage gr ound, ground to pin drivers and internal voltage regulator 50 vdda - - - - - - supply analog voltage 49 vssa - - - - - - supply a nalog voltage ground 59 vdd2_5 , 4 - - - - - - core voltage power supply output (nominally 2.5v) 60 vss2_5 4 - - - - - - core voltage ground output table 2-7. pin functions and signal properties (continued) pin n pin 1 function1 pin 1 function2 pin 1 function3 powered by in/ out pin type 2,3 re set functional description device overview mfr4200 data sheet, rev. 0 36 freescale semiconductor 2.2.3 detailed signal descriptions 2.2.3.1 a[1:6]/xaddr[19:14] ? ami address bus, hcs12 expanded address inputs a[1:6]/xaddr[19:14] are gene ral purpose input pins. their function is selected by the if_sel[0:1] pins. refer to section 3.7, ?host controller interfaces ? for more information. the pins can be configured to enable or disable either pullup or pulldown resistors on the pins. (see section 3.2.3.2.5, ?host interface pins pullup/down enable register (hipper) ? and section 3.2.3.2.6, ?host interface pins pullup/down control register (hippcr) ?.) a[1:6] are ami interface address signals. a1 is the lsb of the ami address bus. xaddr[19:14] are hcs12 interface expanded address lines. xaddr14 is the lsb of the hcs12 interface expanded address lines. 2.2.3.2 a[7:9]/acs[0:2] ? ami address bus, hcs12 expanded address inputs a[7:9]/acs[0:2] are general purpose input pins. their f unction is selected by th e if_sel[0:1] pins. refer to section 3.7, ?host cont roller interfaces ? for more information. the pins ca n be configured to enable or disable either pullup or pul ldown resistors on the pins. 26 vddosc 4 - - - - - - oscillator voltage power supply output (nominally 2.5 v) 23 vssosc 4 - - - - - - oscillator voltage ground output 1 # ? signal is active-low. 2 pc (pullup/down controlled) ? register c ontrolled internal weak pullup/down for a pin in input mode. refer to the following sections for more information: ? section 3.2.3.2.5, ?host interface pins pullup/down enable register (hipper) ? ? section 3.2.3.2.6, ?host interface pins pullup/down control register (hippcr) ? ? section 3.2.3.2.7, ?physical layer pins pullup/down enable register (plpper) ? ? section 3.2.3.2.8, ?physical layer pins pullup/down control register (plppcr) ? pd (pull down) ? internal weak pulldown for a pin in input mode. dc (drive strength controlled) ? register controlled drive stre ngth for a pin in the output mode. refer to the following for mo re information: ? section 3.2.3.2.3, ?host interfac e and physical layer pins drive strength register (hipdsr) ? ? section 3.2.3.2.4, ?physical layer pins drive strength register (plpdsr) ? z ? three-stated pin. od (open drain) ? output pin with open drain. 3 reset state: ? all pins with the pc option have pullup/down resistors disabled. ? all pins with the dc option have full drive strength. 4 no load allowed except for bypass capacitors. table 2-7. pin functions and signal properties (continued) pin n pin 1 function1 pin 1 function2 pin 1 function3 powered by in/ out pin type 2,3 re set functional description signal descriptions mfr4200 data sheet, rev. 0 freescale semiconductor 37 a[7:9] are ami interface address signals. acs[0:2] are hcs12 interf ace address select signals. 2.2.3.3 oe#/acs3 ? ami read output enable, hcs12 address select input. oe#/acs3 is a general purpose input pin. its functi on is selected by the if_sel[0:1] pins. refer to section 3.7, ?host controller interfaces ? for more information. the pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. oe# is the ami interface out put enable signal. this signal controls mfr4200 data output and the state of three-stated data pins d[15: 0] during host read operations. acs3 is an hcs12 interface address select signal. 2.2.3.4 acs[4:5] ? hcs12 address select inputs acs[4:5] are general purpose input pins.their function is selected by the if_sel[0:1] pins. refer to section 3.7, ?host controller interfaces ? for more information. the pins can be configured to enable or disable either pullup or pul ldown resistors on the pins. acs[4:5] are hcs12 interface addr ess select signals. acs5 is the msb of the address select inputs. 2.2.3.5 d[15:0]/pad[0:15] ? ami data bu s, hcs12 multiplexed address/data bus d[15:0]/pad[0:15] are general pur pose input or output pins. their functions are selected by the if_sel[0:1] pins. refer to section 3.7, ?host controller interfaces ? for more information. these pins can be configured to provide e ither high or reduced output drive, and also to enable or disable either pullup or pulldown resistors on the pins. d[15:0] are data signals of the ami interf ace. d0 is the lsb of the ami data bus. pad[0:15] are hcs12 interface multiplexed address/data signals in the hcs12 host interface mode of operation. pad0 is the lsb of the hcs12 address/data bus. 2.2.3.6 ce#/lstrb ? ami chip se lect, hcs12 low-byte strobe the function of this pin is selected by if_sel[0:1] pins. section 3.7, ?host controller interfaces ? for more information. the pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. ce# is an ami interface transfer size input signal. it indicate s the size of the request ed data transfer in the current bus cycle. lstrb is an hcs12 interface low-byte strobe input signal. it indicates the type of bus access. device overview mfr4200 data sheet, rev. 0 38 freescale semiconductor 2.2.3.7 we#/rw_cc# ? ami write enable, hcs12 read/write select the function of this pi n is selected by if_sel[0:1] pins. refer to section 3.7, ?host controller interfaces ? for more information. the pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. we# is an ami interface write select signal. it strobes the valid data provided by the host on the d[15:0] pins during write operations to the mfr4200 memory. rw_cc# is an hcs12 interface read/write input signal. it indicates the direction of data transfer for a transaction. 2.2.3.8 eclk_cc ? hcs12 clock input eclk_cc is the hcs12 interface clock input signal. the input clock frequency can be up to 8 mhz in the hcs12 mode of the external interface block. the pin can be configured to enab le or disable either a pullup or pulldown resistor on the pin. 2.2.3.9 bgt/dbg2/if_sel0 ? bus guardian tick, debug strobe point 2, host interface selection 0 bgt is a bus guardian tick clock output signal provided from the cc . if a bus guardian device is not used in an application, this pin may be left open. bgt is active, irrespective of which physical layer is selected. if the rs485 driver type is selected, this pin is not used. this signal should be connect ed to the bus guardian on each channel. the pin can be configured to provide either high or reduced output drive. dbg2 is debug strobe point output 2. the function output on this pin is selected by the debug port control register. refer to section 3.10, ?debug port ? for more information. if_sel0 is the cc external interf ace selection input signal. refer to table 2-1 for the selection coding. note the if_sel[0:1] signals are inputs dur ing the internal reset sequence and are latched by the internal reset signal level. while the if_sel0 value is being la tched, the output drive control is disabled and the internal pulldown r esistor is connect ed to the pin. as the if_sel[0:1] signals share pins with physical laye r interface signals, pullup/down devices must be u sed for selection. recommended pullup/down resistor values for th e if_sel[0:1] inputs are given in section 2.4.2, ?recommended pullup/down resistor values ?. 2.2.3.10 mt/clk_s1 ? bus guardian ma crotick, clock output select 1 mt is a bus guardian macrotick out put signal from the cc. if a bus guardian device is not used in an application, this pi n may be left open. signal descriptions mfr4200 data sheet, rev. 0 freescale semiconductor 39 mt is active, irrespective of which physical layer is select ed. if the rs485 driver type is selected, this pin is not used. this signal should be connected to the bus guardi ans on each channel. the pin can be configured to provide either high or reduced output drive. clk_s1 is the clkout clock frequency selection input signal. see table 2-2 . note clk_s[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. while the clk_s1 value is being la tched, the output drive control is disabled and the internal pulldown r esistor is connect ed to the pin. as clk_s[0:1] signals share pins wi th physical layer interface signals, pullup/down devices must be u sed for the selection. recommended pullup/down resistor values for th e clk_s[0:1] inputs are given in section 2.4.2, ?recommended pullup/down resistor values ?. 2.2.3.11 arm/dbg1/clk_s0 ? bus guardian arm, debug strobe point 1, clock output select 0 arm is an output signal from the cc to a bus guard ian. if a bus guardian device is not used in an application, this pi n may be left open. arm is active, irrespective of whic h physical layer is select ed. if the rs485 driver type is selected, this pin is not used. this signal should be connect ed to the bus guardian on each channel. the pin can be configured to provide either high or reduced output drive. dbg1 is the debug strobe point output 1. the function output on this pin is selected by the debug port control register. refer to section 3.10, ?debug port ? for more information. clk_s0 is the clkout clock frequency selection input signal. see table 2-2 . note clk_s[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. while the clk_s0 value is being la tched, the output drive control is disabled and the internal pulldown r esistor is connect ed to the pin. as clk_s[0:1] signals share pins wi th physical layer interface signals, pullup/down devices must be u sed for selection. recommended pullup/down resistor values for the clk_s[0:1] inputs are given in the section 2.4.2, ?recommended pullup/down resistor values ?. device overview mfr4200 data sheet, rev. 0 40 freescale semiconductor 2.2.3.12 rxd_bg[1:2]/rxd[1:2]_485 ? phy received data, rs485 received data the function of this pi n is selected by the scm[0:1] bits in the mcr0 register. refer to section 3.2.3.2.1, ?module configuration register 0 (mcr0) ? for more information. the pins can be configured to enable or disable either pullup or pulldown resistors on the pins. rxd_bg[1:2] are bus driver receive data input si gnals if the flexray optical/electrical phy is configured: rxd_bg1 is the input to the cc from physical layer channel 1. rxd_bg2 is the input to the cc from physical layer channel 2. rxd[1:2]_485 are bus driver receive data input signals if the rs 485 driver type is configured: rxd1_485 is the input to the cc from physical layer channel 1 rxd2_485 is the input to the cc from physical layer channel 2. 2.2.3.13 txen[1:2]#/txe[1:2]_485# ? ph y transmit enable, rs485 transmit enable txen[1:2]# are bus driver transmit enable output signals if the flexray optical/electrical phy is configured: txen1# is the output of the cc to physical layer channel 1 txen2# is the output of the cc to physical layer channel 2. txe[1:2]_485# are bus driver transmit enable output signals if the rs 485 driver type is configured: txe1_485# is the output of the cc to the physical layer channel 1. txe2_485# is the output of the cc to the physical layer channel 2. refer to figure 2-10 for an example rs485 bus driver co nnection using external glue logic. the pins can be configured to provid e either high or reduced output drive. 2.2.3.14 txd_bg1/txd1_485/ if_sel1 ? ph y transmit data 1, rs485 transmit data 1, host interface selection 1 the function of this pi n is selected by the scm[0:1] bits in the mcr0 register. refer to section 3.2.3.2.1, ?module configuration register 0 (mcr0) ? for more information. the pins can be configured to provide either high or reduced output drive. txd_bg[1:2] are bus driver transm it data output signals if the fl exray optical/electrical phy is configured: txd_bg1 is the output of the cc to physical layer channel 1 txd_bg2 is the output of the cc to physical layer channel 2. txd[1:2]_485 are bus driver transm it data output signals if the rs 485 driver type is configured: txd1_485 is the output of the cc to physical layer channel 1. txd2_485 is the output of the cc to physical layer channel 2. signal descriptions mfr4200 data sheet, rev. 0 freescale semiconductor 41 if_sel1 is the cc external interf ace selection input signal. refer to table 2-1 for the selection coding. note if_sel[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. while the if_sel1 level is being la tched, the output drive control is disabled and the internal pulldown r esistor is connect ed to the pin. as if_sel[0:1] signals sh are pins with physical layer interface signals, pullup/down devices must be u sed for the selection. recommended pullup/down resistor values for th e if_sel[0:1] inputs are given in section 2.4.2, ?recommended pullup/down resistor values ?. 2.2.3.15 txd_bg2/txd2_485 ? phy transmit data 2, rs485 transmit data 2 the function of this pi n is selected by the scm[0:1] bits in the mcr0 register. refer to section 3.2.3.2.1, ?module configuration register 0 (mcr0) ? for more information. txd_bg[1:2] are bus driver transm it data output signals if the fl exray optical/electrical phy is configured: txd_bg1 is the output of the cc to physical layer channel 1. txd_bg2 is the output of the cc to physical layer channel 2. txd[1:2]_485 are bus driver transm it data output signals if the rs 485 driver type is configured: txd1_485 is the output of the cc to the physical layer channel 1. txd2_485 is the output of the cc to the physical layer channel 2. 2.2.3.16 bgen[1:2] ? bus guardian enable the cc monitors the schedule of bus guardians ope rations by checking the bgen[1:2] input signals provided by bus guardians: bgen1 is the input from the phys ical layer channel 1 to the cc. bgen2 is the input from the phys ical layer channel 2 to the cc. if the rs485 driver type is confi gured, the bgen[1:2] input s are not used and may be left open, but it is recommended to connect thes e pins to the logic "0" or logic "1" le vel either by enabling either pullup or pulldown resistors or by using external components. the pins can be confi gured to enable or disable either pullup or pulldown resistors on the pins. 2.2.3.17 clkout ? clock output clkout is an external continuous clock output signa l. the frequency of clkout is selected by the clk_s[0:1] pins. the clkout signal is always ac tive after power-up of the cc, in all cc states including the hard reset state. the pin can be configured to provide either high or reduced output drive. device overview mfr4200 data sheet, rev. 0 42 freescale semiconductor as the clkout signal can be disabled during internal resets, refer to section 2.4.4, ?external output clock ? for more information on clkout generation during external hard and internal resets . 2.2.3.18 reset# ? external reset reset# is an active-low control signal that acts as an input to initialize the cc to a known startup state. 2.2.3.19 int_cc# ? interrupt output int_cc# is an ami and hcs12 inte rfaces interrupt request output signa l. the cc may request a service routine from the host to run. the interrupt is indicate d by the logic level: it is asserted if the int_cc# outputs a logic "0" and negate d if it outputs a logic "1". the pin can be configured to provid e either high or reduced output drive. 2.2.3.20 test the test pin must be tied to vss in all applications. 2.2.3.21 extal/cc_clk ? crystal driver, external clock pin this pin can act as a crystal driver pin (extal) or as an ex ternal clock input pin (cc_clk). on reset, the device clock is derived from the i nput frequency on this pin. refer to figure 2-3 for pierce oscillator connections and and figure 2-4 for external clock connections. see also chapter 6, ?oscillator (oscv2) ?. 2.2.3.22 xtal ? crystal driver pin xtal is a crystal driver pin. refer to figure 2-3 for pierce oscillator connections and and figure 2-4 for external clock connections. see also chapter 6, ?oscillator (oscv2) ?. figure 2-3. pierce os cillator connections where: q = 40 mhz crystal rb is in the range 1m - 10 mohms rs is a lower value, which can be 0 ohms c1=c2 oscillator supply output capacitor c3 = 220 nf refer to crystal manufacturer?s product specification for recommended values extal xtal vddosc vssosc rs rb q c2 c1 c3 vssosc vssosc mfr4200 signal descriptions mfr4200 data sheet, rev. 0 freescale semiconductor 43 figure 2-4. external clock connections 2.2.4 power supply pins mfr4200 power and ground pins are summarized in table 2-8 and described below. note all vss pins must be connected together in the application. because fast signal tran sitions place high, short- duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as cl ose to the mfr4200 as possible. bypass requirements depend on how heavil y the mfr4200 pins are loaded. table 2-8. mfr4200 power and ground connection summary mnemonic pin number nominal voltage description 64-pin lqfp v dd2_5 59 2.5v internal power and ground generated by internal regulator v ss2_5 60 0v v ddr 20 3.3v external power and ground, supply to supply to pin drivers and internal voltage regulator. v ssr 19 0v v ddx[1:4] 8, 37, 54, 35 3.3v external power and ground, supply to pin drivers. v ssx[1:4] 9, 38, 53, 31 0v v dda 50 3.3v operating voltage and ground for the internal voltage regulator. v ssa 49 0v v ddosc 26 2.5v provides operating voltage and ground for the internal oscillator. this allows the supply voltage to the osci llator to be bypassed independently. internal power and ground generated by internal regulator. v ssosc 23 0v where: g = 40mhz cmos-compatible external oscillator (vddosc-level) extal/cc_clk xtal vddosc vssosc c3 vssosc not connected mfr4200 clkout (left open) device overview mfr4200 data sheet, rev. 0 44 freescale semiconductor 2.2.4.1 vddx, vssx ? power and ground pins for i/o drivers external power and ground for i/o drivers. 2.2.4.2 vddr, vssr ? power and ground pins for i/o driver s and internal voltage regulator external power and ground for i/o drivers a nd input to the internal voltage regulator. note the vddr pin enables the internal 3.3 v to 2.5 v voltage regulator. if this pin is tied to ground, the internal voltage regulator is turned off. 2.2.4.3 vdd2_5, vss2_5 ? core power pins power is supplied to the mfr4200 core through vdd2_5 and vss2_5. this 2.5 v supply is derived from the internal voltage regulator. no static load is allowed on these pins. if vddr is tied to ground, the internal voltage regulator is turned off. note no load is allowed except for bypass capacitors. 2.2.4.4 vdda, vssa ? power supply pins for vreg vdda, vssa are the power supply and ground input pins for the voltage regulator. they also provide the reference voltages for the internal voltage regulator. 2.2.4.5 vddosc, vssosc ? power supply pins for osc vddosc, vssosc provide operati ng voltage and ground for the oscill ator. this allows the supply voltage to the oscillator to be bypassed independent ly. this 2.5v voltage is generated by the internal voltage regulator. note no load is allowed except for bypass capacitors. 2.3 system clock description the internal clock and reset generator block provides the internal clock sign als for the flexray block and all other modules. figure 2-5 shows the clock connections from the crg to all modules. refer to chapter 5, ?clocks and reset generator ? for detailed information on clock generation. system clock description mfr4200 data sheet, rev. 0 freescale semiconductor 45 figure 2-5. clock connections crg extal xtal oscillator clock host interface external clock generator debug strobe tcu transmitter channel a receiver channel a receiver channel b transmitter channel a device overview mfr4200 data sheet, rev. 0 46 freescale semiconductor 2.4 modes of operation 2.4.1 overview the mfr4200 device operates only in one user mode ? the normal mode . in normal mode, different host interfaces can be selected, each with its own associat ed external pin and interface configurations. the device has no low power modes. 2.4.2 recommended pullup/down resistor values as if_sel[0:1] and clk_s[ 0:1] signals share pins with physical layer interface signals, pullup/down devices must be used for selection. recommended pul lup/down resistor values for the if_sel[0:1] and clk_s[0:1] inputs are given in table 2-9 . 2.4.3 host controller interfaces the flexray communication controller can be connected to and controll ed by microcontrollers with two types of interface. the mcu type is selected by the if_sel0 and if_sel1 inputs as shown in section 2.1.3.1, ?interface selection ?. the cc latches the values of the if_sel0 and if_sel1 signals when it leaves the hard reset state. the cc configures the interface for the type of mcu base d on the latched values. the cc latches the values again after it has left the hard reset state (see section 3.9.1, ?hard reset state ?). note if the cc senses an unsupported mode on its if_sel pins, it stops all internal operations, does not perform or respond to any host transactions, stays in configuration mode, and does not integrate into the communication process. the following steps must be ta ken to select a correct mcu interface mode: 1. if_sel0, if_sel1 must be set to ami or to hcs12 mode; 2. the hard reset signal of th e cc must be asserted again. table 2-9. recommended pullup/down resistor values for if_sel[0:1] and clk_s[0:1] inputs io, regulator, and analog supply level ( v dd5 ) pullup resistor 1 1 the listed values are calculated for the mfr4200 physical layer connection where no internal pullup/down resistors are assumed in the electrical phy at the txd_bg1, bgt, arm and mt interface lines. if an electrical phy device has internal pullup/down resistors connected to those signals, then the exter nal pullup/down resistor values must be recalculated to ensure that v il requirements for pulldown resistors or v ih requirements for pullup resistors for the chosen vdd5 are met. refer to section a.1.9, ?i/o characteristics ? for more information on vil, vih and vdd5. pulldown resistor 1 units 3.3v 16 47 kohm 5v 10 47 kohm modes of operation mfr4200 data sheet, rev. 0 freescale semiconductor 47 2.4.4 external output clock the cc provides a continuous extern al output clock signal on the clkout pin; this signal can be either disabled or set to a frequency of 4, 10, or 40 mhz. th e signal is always active after the power-up of the cc, in all cc states including the hard reset state. the clkout signal is disabled during the internal power-on and low voltage reset procedures (refer to chapter 5, ?clocks and reset generator ?, section a.2.2, ?chip power-up and voltage drops ?, and the figures below ( figure 2-6 , figure 2-7 , and figure 2-8 ) for more information). the clk_s[1:0] input pins enable/d isable the clkout signal and select its output frequency in accordance with the table 2-2 . figure 2-6 and figure 2-7 depict the clkout generation during exte rnal hard reset and internal resets. refer to chapter 5, ?clocks and reset generator for more information. figure 2-6. clkout generation during power-on reset por 1 vdd osc clk output internal startup counter 3 internal clk_s[1:0] latches 3 clkout divider internal reset 3 , the divider is based on a counter clkout divider/counter output ~16000 t latching window counter starts counting counter maximum value counter is reset max. count value defined by clk_s[1:0] latched values counter does not count where: ~16000 0 clkout output t uposc 2 notes: 1 for more information on the por, refer to a.2.2, ?chip power-up and voltage drops ?. 2 for more information on the t uposc , refer to a.3, ?reset and oscillator ?. 3 for more information on the internal startup counter, the internal clk_s[1:0] latches, and the clkout divider internal reset signals, refer to chapter 5, ?clocks and reset generator . device overview mfr4200 data sheet, rev. 0 48 freescale semiconductor figure 2-7. clkout generation during low voltage reset lvr 1 internal startup counter 2 internal clk_s[1:0] latches 2 clkout divider internal reset 2 , the divider is based on a counter clkout divider/counter output ~16000 t latching window counter starts counting counter maximum value counter is reset max. count value defined by clk_s[1:0] latched values counter does not count where: ~16000 0 clkout output notes: 1 for more information about the por, refer to a.2.2, ?chip power-up and voltage drops . 2 for more information about the internal startup counte r, the internal clk_s[1:0] latches, and the clkout divider internal reset signals, refer to chapter 5, ?clocks and reset generator . modes of operation mfr4200 data sheet, rev. 0 freescale semiconductor 49 figure 2-8. clkout generation during external hard reset 2.4.5 mfr4200 connection to flexray network figure 2-9 shows an example of connecting a flex ray optical/electrical phy to the mfr4200. figure 2-10 shows how to connect the rs485 transceiver to the cc. external reset internal clk_s[1:0] latches 2 clkout divider internal reset, the divider is based on a counter clkout divider/counter output latching window counter starts counting counter maximum value counter is reset counter does not count where: clkout output reset# pin external reset after internal glitch filter 1 clkout stabilization time 3 10 mhz 4 mhz max 8 t notes: 1 refer to chapter 5, ?clocks and reset generator for more information on the reset glitch filter. 2 for example, running at 10 mhz, then switching to 4 mhz. 3 when the external hard reset signal applied to the reset# pin is negated, the clkout signal frequency is stabilized after maximum 8 t. device overview mfr4200 data sheet, rev. 0 50 freescale semiconductor figure 2-9. example: connecting a flexray optical/electrical phy to the mfr4200 figure 2-10. example: connecting an rs485 phy to the mfr4200 rxd1 txd1 txen1 bge1 mt bgt arm bge2 rxd2 txd2 txen2 mfr4200 bus bus bus bus guardian 1 guardian 2 driver 1 driver 2 rxd_bg1 txd_bg1 txen1 bge1 mt bgt arm bge2 rxd_bg2 txd_bg2 txen1 rxd1 txd1 txen1 bge1 mt bgt arm bge2 rxd2 txd2 txen2 mfr4200 rs485 rs485 transceiver 1 transceiver 2 rxd1_485 txd1_485 txen1_485 bge1 mt bgt arm bge2 rxd2_485 txd2_485 txen2_485 not connected not connected not connected not connected not connected inverter resets and interrupts mfr4200 data sheet, rev. 0 freescale semiconductor 51 note txenn signals for the flexray optical/electrical phy are multiplexed with txenn_485 signals for the rs485 in terfaces. therefore, additional external inverters are required for these signals in the rs485 mode. 2.4.6 power mode no power saving features are implemented in th e mfr4200; the device operates only in power mode. 2.5 resets and interrupts 2.5.1 overview all possible mfr4200 internal interrupt sources are combined and provid ed to the host by means of one available interrupt line: int_cc#. refer to chapter 3, ?mfr4200 flexray communication controller ? for more information on available interrupt sour ces. the type of interrupt is level sensitive. mfr4200 has the following resets: external hard reset input signal reset#. internal power-on and low-voltage resets provided by the internal voltage regulator (refer to chapter 5, ?clocks and reset generator ? and chapter 4, ?dual output voltage regulator (vreg3v3v2) ? for more information). 2.5.2 resets when a reset occurs, mfr4200 registers and control bits are changed to known startup states. refer to the respective module chapters for regist er reset states for information of the different kind of resets and for register reset states. 2.5.2.1 i/o pins refer to chapter 3, ?mfr4200 flexray communication controller ? for configuration of mfr4200 pins out of reset. 2.5.3 interrupt sources all interrupt sources available in the mfr4200 are controlled and indi cated by the following registers: interrupt status register 0 (isr0) interrupt enable register 0 (ier0) startup interrupt status register (sisr) startup interrupt enable register (sier) for more information on interrupt sources, refer to chapter 3, ?mfr4200 flexray communication controller . device overview mfr4200 data sheet, rev. 0 52 freescale semiconductor mfr4200 data sheet, rev. 0 freescale semiconductor 53 chapter 3 mfr4200 flexray communication controller 3.1 introduction this version of the mfr4200 comm unication controller block guide supports mfr4200 devices with the mask numbers 0l60x and 1l60x . 3.1.1 mfr4200 features the mfr4200 provides the following features. the flexray protocol according to flexray protocol working document (pwd) v1.1, with differences described in the mfr4200 pr otocol implementation document (pid) data rate of up to 10 mbit/s on each of two channels flexray frames with up to 254 payload bytes (p adding is used for flexray payload data that exceeds 32-byte data size boundary) one configurable receive fifo configurable counters, status indicators, and interrupts dedicated to error signalling measured value indicators for clock synchronization the status of up to four slots can be obser ved independently of cc receive message buffers configurable error signaling fractional macroticks (mt) supported for clock correction 59 message buffers, each with up to 32 payload bytes message buffers configurable with state or event semantics each message buffer can be configured as a receiv e message buffer, as a transmit message buffer (single or double), or as a part of the receive fifo receive background buffers for each channel the host accesses all buffers by means of three active message bu ffers (active tr ansmit message buffer, active receive message buffer and active receive fifo buffer) filtering for frame id, cycle counter, and channel for receive and transmit message buffers filtering for frame id, channel, a nd message id for the receive fifo maskable interrupt sources pr ovided over one interrupt line two types of host interface: hcs12 in terface and asynchronous memory interfaces minislot action point offset is configurable static slot action point offset is configurable hardware selectable clock output to drive external host devices: disabled/4/10/40 mhz electrical physical layer interf ace compatible with dedicated fl exray physical layer. industry standard rs485 physical laye r interface also available. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 54 freescale semiconductor 3.1.2 mfr4200 implementation parameters and constraints 3.1.2.1 implementation parameters the duration of a microtick (t) is one cc_clk period (25 ns at 40 mhz); a microtick starts with a rising edge of cc_clk. the cc internal initialization procedure lasts for 1025 cycles of the cc_clk clock; it starts after leaving the hard reset state (see section 3.9.1, ?hard reset state ?). after the external hard reset signal on the r eset# pin is negated, the clkout signal frequency is stabilized after 8 t. note refer to section 3.8, ?external 4/10 mhz output clock ? for more information on the clkout output. 3.1.2.2 implementation constraints the maximum external clock frequency is 40 mhz (cc_clk). minislot length down to 2 s (at cc_clk fr equency of 40 mhz) for the dynamic segment. minislot length is configurable (minimum 2 mt). the maximum communication cycle length is 16 ms. collision avoidance symbol length is set to 30 bits. the maximum configurable static slot length is 255 mt. 3.2 memory map and registers 3.2.1 introduction this section describes the memory map, and the content and use of the registers in the host interface module. a memory map of the cc is shown in table 3-1 . the host accesses four t ypes of cc registers: general control registers buffer control, configuration, st atus and filtering register sets fifo acceptance/rejecti on filter register sets fifty-nine (59) configurable message buffers. the host can configure every buffer as a receive message buffer, as a transmit message buffer (s ingle or double), or as a fifo receive message buffer. all buffers are accessible through three active windows mirrored to the memory map: ? one active transmit message buffer ? one active receive message buffer ? one active fifo buffer memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 55 note the cc has two shadow receive messag e buffers per channel (four shadow buffers, in total); these allow recep tion while the host accesses the receive message buffers. one additional shadow message buffer is used for internal operations. therefore, only 59 buffers out of 64 are availabl e to the user as message buffers. 3.2.2 register map summary table 3-1. register map summary register description address (hex) address (dec) hard reset (hex) mnr magic number register 0 0 815 mvr0 module version register 0 2 2 9042 mcr0 module configuration register 0 4 4 8000 mcr1 module configuration register 1 6 6 0 cmcvr current macrotick counter value register 8 8 0 cccvr current cycle counter value register 0a 10 0 psr protocol state register 0c 12 0 isr0 interrupt status register 0 0e 14 0 sisr startup interrupt status register 10 16 0 chier chi error register 12 18 0 ier0 interrupt enable register 0 14 20 0 sier startup inte rrupt enable register 16 22 0 fsizr fifo size register 18 24 0 fafchr fifo acceptance/re jection filter channel register 1a 26 0 fafmidvr fifo acceptance f ilter message id value register 1c 28 0 fafmidmr fifo acceptance filter message id mask register 1e 30 0 frffidvr fifo rejection filter frame id value register 20 32 0 frffidmr fifo rejection filter frame id mask register 22 34 0 rbivecr receive buffer interrupt vector register 24 36 0 tbivecr transmit buffer interrupt vector register 26 38 0 sscir slot status counter incrementation register 28 40 0 sscimr slot status counter interrupt mask register 2a 42 0 mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 56 freescale semiconductor csecnr channel status er ror counter n register, n=[0:1] 2c, 2e 44, 46 0 ticr0cs timer interrupt configuration register 0 cycle set 30 48 0 ticr0mo timer interrupt configuration register 0 macrotick offset 32 50 0 ticr1cs timer interrupt configuration register 1 cycle set 34 52 0 ticr1mo timer interrupt configuration register 1 macrotick offset 36 54 0 dbpcr debug port control register 38 56 0 bgsr bus guardian status register 3a 58 0 dcr delay counter register 3c 60 0 nmvlr network management vector length register 3e 62 0 gnmvnr global network management vector n register, n=[0:5] gnmv0r=40 gnmv1r=42 gnmv2r=44 gnmv3r=46 gnmv4r=48 gnmv5r=4a gnmv0r=64 gnmv1r=66 gnmv2r=68 gnmv3r=70 gnmv4r=72 gnmv5r=74 0 sscnr slot status counter n register, n=[0:7] ssc0r=4c ssc1r=4e ssc2r=50 ssc3r=52 ssc4r=54 ssc5r=56 ssc6r=58 ssc7r=5a ssc0r=76 ssc1r=78 ssc2r=80 ssc3r=82 ssc4r=84 ssc5r=86 ssc6r=88 ssc7r=90 0 ssccnr slot status counter condition n register, n=[0:7] sscc0r=5c sscc1r=5e sscc2r=60 sscc3r=62 sscc4r=64 sscc5r=66 sscc6r=68 sscc7r=6a sscc0r=92 sscc1r=94 sscc2r=96 sscc3r=98 sscc4r=100 sscc5r=102 sscc6r=104 sscc7r=106 0 sssnr slot status selection n register, n= [0:3] sss0r=6c sss1r=6e sss2r=70 sss3r=72 sss0r=108 sss1r=110 sss2r=112 sss3r=114 0 table 3-1. register map summary register description address (hex) address (dec) hard reset (hex) memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 57 ssnr slot status n regi ster, n=[0:7] ss0r=74 ss1r=76 ss2r=78 ss3r=7a ss4r=7c ss5r=7e ss6r=80 ss7r=82 ss0r=116 ss1r=118 ss2r=120 ss3r=122 ss4r=124 ss5r=126 ss6r=128 ss7r=130 0 swctrlr symbol window control register 84 132 0 swsar symbol window status channel a register 86 134 0 swsbr symbol window status channel b register 88 136 0 wmctrlr wakeup mechanism control register 8a 138 0 nssr number of static slots register 8e 142 1 splr static payload length register 90 144 0 mpldr maximum payload length dynamic register 92 146 0 syncfr sync frame register 94 148 0 synchr sync frame header register 96 150 undefined mvr1 module version register 1 98 152 for mask set number: 0l60x ? 0; 1l60x ? 0001 hipdsr host interface pins drive strength register 9a 154 0 plpdsr physical layer pins drive strength register 9c 156 0 hipper host interface pins pullup/down enable register 9e 158 0 hippcr host interface pins pullup/down control register a0 160 0 plpper physical layer pins pullup/down enable register a2 162 0 plppcr physical layer pins pullup/down control register a4 164 0 vregsr voltage regulator status register a6 166 0 bdr bit duration register a8 168 undefined idlr idle detection length register aa 170 undefined nmlr nominal macrotick length register ac 172 undefined bgtr bus guardian tick register ae 174 undefined sslr static slot length register b0 176 undefined table 3-1. register map summary register description address (hex) address (dec) hard reset (hex) mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 58 freescale semiconductor clr cycle length register b2 178 undefined mpclr microticks per cycle low register b4 180 undefined mpchr microticks per cycle high register b6 182 undefined mcldar maximum cycle length deviation register b8 184 undefined tsslr transmit start sequence length register ba 186 undefined swcr symbol window configuration register bc 188 undefined nitcr network idle time confi guration register be 190 undefined csmr coldstart maximum register c0 192 undefined msfr maximum sync frames register c2 194 undefined ldtsr latest dynamic transmission start register c4 196 undefined mslr minislot length register c6 198 undefined msapor minislot action point offset register c8 200 undefined ssapor static slot action point offset register ca 202 undefined mocwcfr maximum odd cycles without clock correction fatal register cc 204 undefined dcar delay compensation channel a register d0 208 undefined dcbr delay compensation channel b register d2 210 undefined lnlr listen timeout with noise length register d6 214 undefined mocwcpr maximum odd cycles without clock correction passive register d8 216 undefined mocr maximum offset correction register da 218 undefined mrcr maximum rate correction register dc 220 undefined cddr cluster drift damping register de 222 undefined socctr start of offset correction cycle time register e0 224 undefined wustxir wakeup symbol tx idle register ea 234 0 wustxlr wakeup symbol tx low register ec 236 0 synfafmr sync frame acceptance filter mask register ee 238 undefined synfafvr sync frame acceptance filter value register f0 240 undefined synfrfr sync frame rejection filter register f2 242 undefined eocr external offset correction register f4 244 undefined ercr external rate correction register f6 246 undefined table 3-1. register map summary register description address (hex) address (dec) hard reset (hex) memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 59 eccr external correction control register f8 248 undefined afbfrid active fifo buffer frame id register 100 256 undefined afbccplr active fifo bu ffer cycle counter and payload length register 102 258 undefined afbcrcr active fifo buffer he ader crc register 104 260 undefined afbdatanr active fifo buffer data n register, n=[0:15] arfbdata0r=106 ? arfbdata15r=124 arfbdata0r=262 ? arfbdata15r=292 undefined afbmbssvr active fifo buffer message buffer slot status vector register 126 294 undefined arbfrid active receive buffer frame id register 140 320 undefined arbccplr active receive buffer cycle counter and payload length register 142 322 undefined arbcrcr active receive buffer header crc register 144 324 undefined arbdatanr active receive buffer data n register, n=[0:15] arbdata0r=146 ? arbdata15r=164 arbdata0r=326 ? arbdata15r=356 undefined arbmbssvr active receive buffer message buffer slot status vector register 166 358 undefined atbfrid active transmit buffer frame id register 180 384 undefined atbccplr active transmit buffer cycle counter and payload length register 182 386 undefined atbcrcr active transmit buffer header crc register 184 388 undefined atbdatanr active transmit buffer data n register, n=[0:15] at b data 0 r = 1 8 6 ? atbdata15r=1a4 at b data 0 r = 3 9 0 ? atbdata15r=420 undefined atbmbssvr active transmit buffer message buffer slot status vector register 1a6 422 undefined bufcsnr message buffer control, configuration and status n register, n=[0:58] bufcs0r=200 bufcs1r=204 ? bufcs57r=2e4 bufcs58r=2e8 bufcs0r=512 bufcs1r=516 ? bufcs57r=740 bufcs58r=744 iflg, iena, cfg and valid bits are reset to 0; others are undefined ccfnr cycle counter filter n register, n=[0:58] ccf0r=202 ccf1r=206 ? ccf57r=2e6 ccf58r=2ea. ccf0r=514 ccf1r=518 ? ccf57r=742 ccf58r=746 undefined ccfcr clock correction failed counter register 326 806 undefined ehlr error handling level register 328 808 undefined table 3-1. register map summary register description address (hex) address (dec) hard reset (hex) mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 60 freescale semiconductor 3.2.3 register descriptions a condensed overview of all registers is provided in section 3.2.2, ?register map summary ? note all registers not shown in the cc memory map registers are not implemented in hardware. any read operation on bits marked as ? reserved ? will return an undefined value (either ?1? or ?0?). the host must take care that bits marked as ?re served? are set to 0 when writing. the reset value indicated for each regi ster is the value that the register has after a hard reset operation. meaning of the bit field char acter in the registers layout: ? ? r ? indicates that the bit-field may be read by host ? ? w ? denotes that the bit-field may be updated by host ? ? h ? means that the bit-field is updat ed by the communication controller rcvr rate correction value register 32a 810 undefined ocvr offset correction value register 32c 812 undefined emcr even measurement counter register 33c 828 undefined omcr odd measurement counter register 33e 830 undefined emanr even measurement channel a n register, n=[0:15] ema0r=340 ? ema15r=35e ema0r=832 ? ema15r=862 undefined embnr even measurement channel b n register, n=[0:15] emb0r=360 ? emb15r=37e emb0r=864 ? emb15r=894 undefined esfidnr even sync id n register, n=[0:15] eid0r=380 ? eid15r=39e eid0r=896 ? eid15r=926 undefined omanr odd measurement channel a n register, n=[0:15] oma0r=3a0 ? oma15r=3be oma0r=928 ? oma15r=958 undefined ombnr odd measurement channel b n register, n=[0:15] omb0r=3c0 ? omb15r=3de omb0r=960 ? omb15r=990 undefined osfidnr odd sync frame id n register, n=[0:15] osfid0r=3e0 ? osfid15r=3fe osfid0r=1008 ? osfid15r=1022 undefined table 3-1. register map summary register description address (hex) address (dec) hard reset (hex) memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 61 combinations such as ? rh ?, ? rw ? or ? rwh ? appear in the text indicating the different access possibilities. an additional asterisk ? * ? indicates an exceptional behavior, i.e. under which conditions the host is allowed to write a ? rw ? or ? rwh ? bit-field, etc. in such cases, refer to the detailed bit-field description. descriptions of configuration regist ers specify the possible range of values in square brackets ? [,]. note the configuration registers? possible ra nges of values, specified in square brackets [ : ], denote only the mfr 4200 implementation constraints. not every configuration supported by the mfr4200 implementation is necessarily a valid conf iguration of an appli cation network. for more information about configuration c onstraints, refer to the pwd: configuration constraints notations chapter. a key to the register diagrams is shown in figure 3-1 . figure 3-1. key to register diagrams 3.2.3.3.1 bit dura tion register (bdr) flexray protocol related parameter ? gdbit address0xa8 reset undefined state 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved bd6 bd5 bd4 bd3 bd2 bd1 bd0 r rw* rw* rw* rw* rw* rw* rw* section number register register full name register short name register reset bit number bit access bit name value/state flexray protocol related parameter address scheme mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 62 freescale semiconductor 3.2.3.1 controller?s constants registers 3.2.3.1.1 module versio n register 0 (mvr0) address 0x2 reset 0x9042 the read-only mvr0, together with mvr1 (see fo llowing section), holds th e version number of the implementation. the mvr0 cont ains the following fields: pda[0:7] denotes the device partid1. minfr[0:3] denotes the minor release of the flexray core in the mfr4200 device. mjfr[0:3] denotes the major release of the flexray core in the mfr4200 device. 3.2.3.1.2 module versio n register 1 (mvr1) address 0x98 reset the read-only mvr1, together with mvr0 (see prev ious section), holds the version number of the implementation. the mvr1 contains: 15 14 13 12 11 10 9 8 mjfr3 mjfr2 mjfr1 mjfr0 mi nfr3 minfr2 minfr1 minfr0 rrrrrrrr 76543210 pda7 pda6 pda5 pda4 pda3 pda2 pda1 pda0 rrrrrrrr figure 3-2. module version register 0 device mask set number reset value mfr4200 0l60x 0x0000 mfr4200 1l60x 0x0001 15 14 13 12 11 10 9 8 pdb7 pdb6 pdb5 pdb4 pdb3 pdb2 pdb1 pdb0 rrrrrrrr 76543210 mjmr3 mjmr2 mjmr1 mjmr0 minmr3 minmr2 minmr1 minmr0 rrrrrrrr figure 3-3. module version register 1 memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 63 pdb[0:7] denotes the device partid2. minmr[0:3] denotes the minor release of the mfr4200 device. mjmr[0:3] denotes the major re lease of the mfr4200 device. 3.2.3.1.3 magic numb er register (mnr) address 0x0 reset 0x0815 this read-only register contains the arbitrary value 0x0815; it is used for endianess and memory map address offset checks. note the mnr contains 0x0000 while the contro ller is initializing after leaving the hard reset state. only after this in itialization is comple ted, does it contain the value 0x0815. after the controller leav es the hard reset state, the host must wait until the initialization is co mpleted before reading or writing to the controller. the initializati on takes 1025 cycles (cc_clk) after de-assertion of the hard reset. during the internal initialization pro cedure time, the hos t must not access any cc register except mnr (see section 3.2.3.1.3, ?magic number register (mnr) ?), which acknowledges the completion of the internal initialization procedure. 15 14 13 12 11 10 9 8 mn15 mn14 mn13 mn12 mn11 mn10 mn9 mn8 rrrrrrrr 76543210 mn7 mn6 mn5 mn4 mn3 mn2 mn1 mn0 rrrrrrrr figure 3-4. magic number register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 64 freescale semiconductor 3.2.3.2 configuration registers 3.2.3.2.1 module configura tion register 0 (mcr0) address 0x4 reset 0x8000 note setting the config bit and writing to other bits in this register can be done in separate instructions only. trying to set config and change other bits at the same time will cha nge config only ? the ot her bits will not be changed. clearing config a nd writing to other bits in the mcr0 can be done simultaneously in one instruction. diagstop ? diagnosis stop state bit when this bit is set by the host, the cc imme diately enters the diagnosis stop state. any ongoing transmission or reception is abor ted, and synchronization with the fl exray communication bus is lost. when this bit is cleared by the host, the controller enters th e configuration state. 1 ? the cc is in the diagnosis stop state. 0 ? the cc is not in the diagnosis stop state. scm0, scm1 ? serial communication mode bits 0 and 1 these bits define the type of bus driver connected to the controller. it can be written during the configuration state only. 15 14 13 12 11 10 9 8 config reserved reserved reserved reserved reserved cbe cae rwh r r r r r rw* rw* 76543210 reserved ensynff nsync scm1 scm0 reserved diagstop reserved r rw* rh rw* rw* r rw r figure 3-5. module configuration register 0 table 3-2. bus driver type selection driver type scm1 scm0 rs485 (idle state coded as ?0?) 0 0 optical/electrical phy 0 1 ?10 rs485 (idle state coded as ?1?) 1 1 memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 65 note it is not possible to mix different rs485?s in a cluster or per channel, or to mix rs485 and optical/electrical phy. nsync ? node synchronized this read-only bit is set when the c ontroller enters the normal state in th e course of startup or reintegration. the nsync is set by the cc in the nit preceding a transition to normal opera tion. the nsync is cleared by the cc in the nit, prior to switching to the normal passive state (the ?y ellow? error state; see section 3.2.3.6.5, ?error handling level register (ehlr) ?) or the diagnosis stop state (the ?red? error state; see section 3.2.3.6.5, ?error handli ng level register (ehlr) ?), due to? ?the correction value exceeding mrcr (see section 3.2.3.3.25, ?maximum rate correction register (mrcr) ?) ?the offset correction value exceeding mocr (see section 3.2.3.3.24, ?maximum offset correction register (mocr) ?) ?the ccfcr value (see section 3.2.3.6.4, ?clock correction fa iled counter register (ccfcr) ?) exceeding mocwcpr (see section 3.2.3.5.3, ?maximum odd cycles without clock correction passive register (mocwcpr) ?) or mocwcfr (see section 3.2.3.5.2, ?maximum odd cycles without clock correction fatal register (mocwcfr) ). 1 ? node is synchronized to cluster. 0 ? node is not synchronized to cluster. ensynff ? enable sync frame filters this bit enables/disables acceptance and rejection filtering fo r sync frames (see section 3.2.3.8.1, ?sync frame acceptance filter va lue register (synfafvr) ?, section 3.2.3.8.2, ?sync frame acceptance filter mask register (synfafmr) ? and section 3.2.3.8.3, ?sync frame reje ction filter register (synfrfr) ?). 1 ? sync frames are used for the clock synchronization only when they pass the acceptance filter and are not rejected by the rejection filter. 0 ? sync frames are used for the cl ock synchronization independently of the acceptance and rejection filter. cae ? channel a enable this bit enables channel a. it can be written during the configuration state only. 1 ? channel a is enabled. 0 ? channel a is disabled. cbe ? channel b enable this bit enables channel b. it can be written during the configuration state only. 1 ? channel b is enabled. 0 ? channel b disabled. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 66 freescale semiconductor config ? configuration state bit when the host sets this bit, the cc immediately enters the configuration state. the controller aborts any ongoing transmission or recep tion and abandons synchronization to the flexray cluster. when the host clears this bit, the controller resumes normal operation (see section 3.9.2, ?configuration state ?). after a hard reset, the controller automatically ente rs the configuration state (config bit set). 1 ? configuration state. 0 ? normal operation. 3.2.3.2.2 module configura tion register 1 (mcr1) address 0x6 reset 0x0 mate ? media access test enable this flag enables the media access test in the mfr 4200 bus guardian (bg) monitor. this flag may be written in the configuration state only. 1 ? media access test is enabled. 0 ? media access test is disabled. bgsmswe ? bg schedule monitoring symbol window enable this flag determines the behavior of the mfr 4200 bus guardian schedule m onitor during the symbol window. it may be written in the configuration state only. 1 ? bg is expected to be open during sy mbol window of the communication cycle. 0 ? bg is expected to be closed during symbol window of the communication cycle. bgsmdse ? bg schedule monitoring dynamic segment enable this flag determines the behavi or of the mfr4200 bus guardian moni tor during the dynamic segment of the communication cycle. it may be wr itten in the configuration state only. 1 ? bg expected to be open during dynami c segment of the communication cycle. 0 ? bg expected to be closed during dyna mic segment of the communication cycle. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved aytg arl csi rrrrrrw*rw*rw* 76543210 reserved ecse bgsmdse bgsmswe reserved mate reserved reserved r rw* rw* rw* r rw* r r figure 3-6. module configuration register 1 memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 67 ecse ? external clock synchronization enable this configuration flag enables/disa bles the external clock synchroniza tion. it can be written during the configuration state only. 1 ? external clock synchronization is enabled. 0 ? external clock synchronization is disabled. csi ? coldstart inhibit mode the node can be prevented from in itializing the tdma communication schedule by setting the csi bit to ?1? in the configuration state. it can be written during the c onfiguration state only. 1 ? node is in coldstart inhibit mode. 0 ? node is not in coldstart inhibit mode. arl ? allow red level if this bit is set, the transition to the red error handl ing level (diagnosis stop state) due to clock sync errors is allowed. it may be written in the configuration state only. 1 ? error handling level red is allowed (t he cc enters the diagnosis stop state). 0 ? error handling level red is prohibited (the cc enters the configuration state). aytg ? allow yellow to green if this bit is set, the transition fr om the yellow error handling level to the green error handling level is allowed. it may be written in the configuration state only. 1 ? transition from yellow to green is allowed. 0 ? transition from yellow to green is prohibited. 3.2.3.2.3 host interface and physical layer pi ns drive strength register (hipdsr) address 0x9a reset 0x0 this register controls the drive strengt h of the mfr4200 pins identified in figure 3-7 . 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved int_cc# clkout arm/dbg1/ clk_s0 mt/clk_s1 bgt/dbg2/ if_sel0 pad[0:15]/ d[15:0] r r rw rw rw rw rw rw figure 3-7. host interface pins drive strength register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 68 freescale semiconductor 1 ? pin drive strength is partial (see appendix a.1.9, ?i/o characteristics ?). 0 ? pin drive strength is full (see appendix a.1.9, ?i/o characteristics ?). 3.2.3.2.4 physical layer pins dr ive strength register (plpdsr) address 0x9c reset 0x0 this register controls the drive strengt h of the mfr4200 pins identified in figure 3-8 . 1 ? pin drive strength is partial (see section a.1.9, ?i/o characteristics ?). 0 ? pin drive strength is full (see section a.1.9, ?i/o characteristics ?). 3.2.3.2.5 host interface pins pullup/ down enable r egister (hipper) address 0x9e reset 0x0 this register enables the pullups and pul ldowns on mfr4200 pins identified in figure 3-9 . the pullup/down state is contro lled by the hippcr (see section 3.2.3.2.6, ?host interface pins pullup/down control register (hippcr) ?). 1 ? pullup/down resistor enabled. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved rese rved reserved txd_bg2/ txd2_485 txd_bg1/ txd1_485/ if_sel1 txen2#/ txe2_485# txen1#/ txe1_485# r r r r rw rw rw rw figure 3-8. physical layer pins drive strength register 15 14 13 12 11 10 9 8 eclk_cc we#/ rw_cc# ce#/lstrb d[15:0]/ pad[0:15] acs5 acs4 oe#/acs3 a9/acs2 rw rw rw rw rw rw rw rw 76543210 a8/acs1 a7/acs0 a6/ xaddr14 a5/ xaddr15 a4/ xaddr16 a3/ xaddr17 a2/ xaddr18 a1/ xaddr19 rw rw rw rw rw rw rw rw figure 3-9. host interface pins pullup/down enable register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 69 0 ? pullup/down resistor disabled. 3.2.3.2.6 host interface pins pullup/ down control r egister (hippcr) address 0xa0 reset 0x0 this register controls the pullups a nd pulldowns on mfr4200 pins identified in figure 3-10 . these functions can be enabled/di sabled by the hipper (see section 3.2.3.2.5, ?host interface pins pullup/down enable register (hipper) ?). 1 ? pullup selected. 0 ? pulldown selected. 3.2.3.2.7 physical layer pins pullup /down enable register (plpper) address 0xa2 reset 0x0 this register enables the pullups and pul ldowns on mfr4200 pins identified in figure 3-11 . the pullup/down state is cont rolled by the plppcr (see section 3.2.3.2.8, ?physical layer pins pullup/down control register (plppcr) ?). 1 ? pullup/down enabled. 0 ? pullup/down disabled. 15 14 13 12 11 10 9 8 eclk_cc we#/ rw_cc# ce#/lstrb d[15:0]/ pad[0:15] acs5 acs4 oe#/acs3 a9/acs2 rw rw rw rw rw rw rw rw 76543210 a8/acs1 a7/acs0 a6/ xaddr14 a5/ xaddr15 a4/ xaddr16 a3/ xaddr17 a2/ xaddr18 a1/ xaddr19 rw rw rw rw rw rw rw rw figure 3-10. host interface pins pullup/down control register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved bgen2 bgen1 rxd_bg2/ rxd2_485 rxd_bg1/rx d1_485 r r r r rw rw rw rw figure 3-11. physical layer pins pullup/down enable register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 70 freescale semiconductor 3.2.3.2.8 physical layer pins pullup /down control r egister (plppcr) address 0xa4 reset 0x0 this register controls the pullups a nd pulldowns on mfr4200 pins identified in figure 3-12 . these function can be enabled/di sabled by the plpper (see section 3.2.3.2.7, ?physical layer pins pullup/down enable register (plpper) ?). 1 ? pullup selected. 0 ? pulldown selected. 3.2.3.2.9 voltage regulato r status regist er (vregsr) address 0xa6 reset this register indicates the occurrence of internal low-voltage and/or power-on reset events caused by power-on of mfr4200 device or supply voltage dist urbances. the low-voltage status and power-on status bits do not cause an interrupt over the int_cc# pin; therefore, the host may read this register to check the status. the host clears any status bit in vregsr by re ading vregsr. the cc sets a status bit in the vregsr again when it detects the condition for that bit. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved bgen2 bgen1 rxd_bg2/ rxd2_485 rxd_bg1/rx d1_485 r r r r rw rw rw rw figure 3-12. physical layer pins pullup/down control register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved reserved reserved low-voltage status power-on status rrrrrrrwhrwh figure 3-13. voltage regulator status register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 71 low-voltage status, power-on status 1 ? mfr4200 has been reset internally due to re set conditions sensed by the voltage regulator. 0 ? mfr4200 has not been reset internally. note low-voltage and power-on events generated by the mfr4200 voltage regulator cause the internal mfr4200 reset with the same consequences as in the case of an external hard reset. therefore, changes to the vregsr bits can be read by the host only after the mfr4200 leaves the internal reset state. 3.2.3.3 control registers 3.2.3.3.1 bit durati on register (bdr) flexray protocol related parameter ? gdbit address 0xa8 reset undefined state this register controls the number of microticks per bit. writing this register is possible only during the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved bd6 bd5 bd4 bd3 bd2 bd1 bd0 r rw* rw* rw* rw* rw* rw* rw* figure 3-14. bit duration register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 72 freescale semiconductor 3.2.3.3.2 delay compensation channel a regi ster (dcar) flexray protocol related parameter ? pdelaycompensation[a] address 0xd0 reset undefined state this register holds the value used to compensate for reception delays on channel a in microticks. the register can be written during the co nfiguration state only. the value of this register must be within the range [0:127]. 3.2.3.3.3 delay compensation channel b regi ster (dcbr) flexray protocol related parameter ? pdelaycompensation[b] address 0xd2 reset undefined state this register holds the value used to compensate for reception delays on channel b in microticks. the register can be written during the co nfiguration state only. the value of this register must be within the range [0:127]. 15 14 13 12 11 10 9 8 dca15 dca14 dca13 dca12 dca11 dca10 dca9 dca8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 dca7 dca6 dca5 dca4 dca3 dca2 dca1 dca0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-15. delay compensation channel a register 15 14 13 12 11 10 9 8 dcb15 dcb14 dcb13 dcb12 dcb11 dcb10 dcb9 dcb8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 dcb7 dcb6 dcb5 dcb4 dcb3 dcb2 dcb1 dcb0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-16. delay compensation channel b register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 73 3.2.3.3.4 cluster drift damping register (cddr) flexray protocol related parameter ? pclusterdriftdamping address 0xde reset undefined state this register defines the value used, in clock s ynchronization, to minimize th e accumulation of rounding errors. this register can be written in the configuration state only. the register value is given in microticks and must be within the range [1:15]. 3.2.3.3.5 maximum sync fr ames register (msfr) flexray protocol related parameter ? gsyncnodemax address 0xc2 reset undefined state this register holds the maximum num ber of sync frames that can be transmitted on either channel in a network, including a node?s own sync fr ame. the host may modify this regi ster in the configuration state only. the value of this register must be within the range [2:15]. 15 14 13 12 11 10 9 8 cdd15 cdd14 cdd13 cdd12 cdd11 cdd10 cdd9 cdd8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 cdd7 cdd6 cdd5 cdd4 cdd3 cdd2 cdd1 cdd0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-17. cluster dr ift damping register 15 14 13 12 11 10 9 8 msf15 msf14 msf13 msf12 msf11 msf10 msf9 msf8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 msf7 msf6 msf5 msf4 msf3 msf2 msf1 msf0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-18. maximum sync frames register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 74 freescale semiconductor 3.2.3.3.6 nominal macrotic k length register (nmlr) flexray protocol related parameter ? pmicropermacronom address 0xac reset undefined state this register defines the integer number of microticks per nominal macrotick, according to equation 3-1 . nmlr = int (cycle length in t / clr) eqn. 3-1 writing this register is possibl e only in the configuration state. 3.2.3.3.7 microticks per cy cle low register (mpclr) address 0xb4 reset undefined state the mpchr and mpclr are described in the following section. the mpclr can be written duri ng the configuration state only. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 nml7 nml6 nml5 nml4 nml3 nml2 nml1 nml0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-19. nominal macrotick length register 15 14 13 12 11 10 9 8 mpcl15 mpcl14 mpcl13 mpcl12 mpcl11 mpcl10 mpcl9 mpcl8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 mpcl7 mpcl6 mpcl5 mpcl4 mpcl3 mpcl2 mpcl1 mpcl0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-20. microticks per cycle low register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 75 3.2.3.3.8 microticks per cy cle high register (mpchr) address 0xb6 reset undefined state the mpchr and mpclr define the num ber of microticks per cycle. wr iting these registers is possible only in the configuration state. the relationship betw een registers mpchr, mpclr, and clr is given by equation 3-2 . mpchr * 2^16 + mpclr = (cycle length) ? k * clr eqn. 3-2 where: cycle length = the length of a communication cycle in microticks k = 1 [microtick/macrotick] 3.2.3.3.9 static slot length register (sslr) flexray protocol related parameter ? gdstaticslot address 0xb0 reset undefined state this register defines the number of macroticks per slot. writing this register is possible only in the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 mpch7 mpch6 mpch5 mpch4 mpch3 mpch2 mpch1 mpch0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-21. microticks per cycle high register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 ssl7 ssl6 ssl5 ssl4 ssl3 ssl2 ssl1 ssl0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-22. static slot length register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 76 freescale semiconductor 3.2.3.3.10 number of stat ic slots register (nssr) flexray protocol related para meter ? gnumberofstaticslots address 0x8e reset 0x1 this register defines the number of static slots in a cycle. writing this register is possible only during the configuration state. note the range of possible values for the ns sr is from 0x2 to 0x3ff. this means that at least two static slots must be programmed . 3.2.3.3.11 static payloa d length register (splr) flexray protocol related parameter ? gpayloadlengthstatic address 0x90 reset 0x0 this register defines the maximum data length for stat ic frames in words (1 word = 2 bytes). writing this register is possible only dur ing the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved re served reserved nss10 nss9 nss8 rrrrrrw*rw*rw* 76543210 nss7 nss6 nss5 nss4 nss3 nss2 nss1 nss0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-23. number of static slots register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved spl6 spl5 spl4 spl3 spl2 spl1 spl0 r rw* rw* rw* rw* rw* rw* rw* figure 3-24. static payload length register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 77 3.2.3.3.12 minislot leng th register (mslr) flexray protocol related parameter ? gdminislot address 0xc6 reset undefined state this register defines the minislot length in macroticks. the register can be written during the configuration state only. the value of this register must be within the range [2:63]. 3.2.3.3.13 minislot action poin t offset regi ster (msapor) flexray protocol related parameter ? gdminislotactionpointoffset address 0xc8 reset undefined state this register defines the offset of the action point wi thin the minislot in macrot icks. the register can be written during the configuration state only. the value of this register must be within the range [1:15]. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved msl6 msl5 msl4 msl3 msl2 msl1 msl0 r rw* rw* rw* rw* rw* rw* rw* figure 3-25. minislot length register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved msapo3 msapo2 msapo1 msapo0 r r r r rw* rw* rw* rw* figure 3-26. minislot action point offset register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 78 freescale semiconductor 3.2.3.3.14 static slot action point offset register (ssapor) flexray protocol related parameter ? gdactionpointoffset address 0xca reset undefined state this register defines the offset of the action point in macroticks. the register can be written only during the configuration state. the value of this register must be within the range [1:15]. 3.2.3.3.15 latest dynamic trans mission start register (ldtsr) flexray protocol related parameter ? platesttx address 0xc4 reset undefined state this register defines the cycle time after which dynami c frame transmission can star t. if the cycle time is greater than this register?s value, the controller continues an ongoing dynamic fra me transmission (started before this point in time) and does not start any new dynamic frame transmissions. the latest dynamic transmission start is expressed in macroticks. the re gister can be written only in the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved ssapo3 ssapo2 ssapo1 ssapo0 r r r r rw* rw* rw* rw* figure 3-27. static slot action point offset register 15 14 13 12 11 10 9 8 reserved reserved ldt13 ldt12 ldt11 ldt10 ldt9 ldt8 r r rw* rw* rw* rw* rw* rw* 76543210 ldt7 ldt6 ldt5 ldt4 ldt3 ldt2 ldt1 ldt0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-28. latest dynamic transmission start register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 79 3.2.3.3.16 maximum payload length dynamic register (mpldr) flexray protocol related parameter ? gmaxpayloadlengthdynamic address 0x92 reset 0x0 this register defines the max imum payload length in the dynamic segment, in terms of words (1 word = 2 bytes). this register can be w ritten only during the configuration state. note the value of the maximum payload le ngth dynamic register is used for checking transmit message buffers (see the mdple bit description in section 3.2.3.6.3, ?chi error register (chier) ? and section 3.3.2.7, ?len[6: 0] ? payload length ?). 3.2.3.3.17 symbol window conf iguration register (swcr) flexray protocol related parameter ? gdsymbolwindow address 0xbc reset undefined state this register defines the cycle time in which the symbol window starts . the cycle time is measured in macroticks. this register may be modi fied only in the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved mpld6* mpld5* mpld4* mpld3* mpld2* mpld1* mpld0* r rw* rw* rw* rw* rw* rw* rw* figure 3-29. maximum payload length dynamic register 15 14 13 12 11 10 9 8 reserved reserved swc13 swc12 swc11 swc10 swc9 swc8 r r rw* rw* rw* rw* rw* rw* 76543210 swc7 swc6 swc5 swc4 swc3 swc2 swc1 swc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-30. symbol window configuration register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 80 freescale semiconductor 3.2.3.3.18 network idle time c onfiguration register (nitcr) flexray protocol related parameter ? gdnit address 0xbe reset undefined state this register defines the cycle time in which the network idle time starts. the cycle time is measured in macroticks. the register may be modified in the confi guration state only. this re gister is related to the socctr register (refer to the note in section 3.2.3.3.34, ?start of offset co rrection cycle t ime register (socctr) ?). note since the duration of the nit mu st be longer than or equal to ceil ((1300t + 170t * msfr)/nmlr) + 1 [nominal mt], eqn. 3-3 this register must be configured to, at most clr - nit duration [nominal mt] eqn. 3-4 3.2.3.3.19 cycle length register (clr) flexray protocol related parameter ? gmacropercycle address 0xb2 reset undefined state this register defines the number of macroticks per cycle. writing this register is possible during the configuration state only. the cc uses this register valu e during startup only. 15 14 13 12 11 10 9 8 reserved reserved nitc13 nitc 12 nitc11 nitc10 nitc9 nitc8 r r rw* rw* rw* rw* rw* rw* 76543210 nitc7 nitc6 nitc5 nitc4 nitc3 nitc2 nitc1 nitc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-31. network idle time configuration register 15 14 13 12 11 10 9 8 reserved reserved cl13 cl12 cl11 cl10 cl9 cl8 r r rw* rw* rw* rw* rw* rw* 76543210 cl7 cl6 cl5 cl4 cl3 cl2 cl1 cl0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-32. cycle length register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 81 3.2.3.3.20 maximum cycle length deviation register (mcldar) flexray protocol related parameter ? gdmaxdrift address 0xb8 reset undefined state this register defines the number of microticks for a communicati on cycle of another cc with the maximum deviation of 1500 ppm with respect to the local oscillator. writing this register is possibl e only during the configuration stat e. the value for the mcldar is calculated from equation 3-5 : mcldar = ceil ( cycle_length[t] * 1.5*10-3 ) eqn. 3-5 3.2.3.3.21 external offset correction register (eocr) flexray protocol related parame ter ? pexternoffsetcorrection address 0xf4 reset undefined state this register holds the absolute value of the initial ex ternal offset correction to be applied, together with the internal clock synchronization value (see section 3.2.3.3.23, ?external correction control register (eccr) ?). the host may write this register during the co nfiguration state only. the register value is expressed in microticks. 15 14 13 12 11 10 9 8 reserved reserved reserved reserv ed reserved reserved mclda9 mclda8 rrrrrrrw*rw* 76543210 mclda7 mclda6 mclda5 mclda4 mclda3 mclda2 mclda1 mclda0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-33. maximum cycle length deviation register 15 14 13 12 11 10 9 8 eoc15 eoc14 eoc13 eoc12 eoc11 eoc10 eoc9 eoc8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-34. external offset correction register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 82 freescale semiconductor 3.2.3.3.22 external rate correction register (ercr) flexray protocol related parameter ? pexternratecorrection address 0xf6 reset undefined state this register holds the absolute value of the initial ex ternal rate correction to be applied, together with the internal clock synchronization value (see section 3.2.3.3.23, ?external correction control register (eccr) ?). the host may write this register in the configuration state only. the register valu e is expressed in microticks. 3.2.3.3.23 external correcti on control register (eccr) address 0xf8 reset undefined state note this register must be set before th e nit start of communication cycle x, in order to affect the clock correction in the communication cycle x+1. eoce ? external offset correction enable 0 ? external offset correction disabled. 1 ? external offset correction enabled. 15 14 13 12 11 10 9 8 ecr15 ecr14 ecr13 ecr12 ecr11 ecr10 ecr9 ecr8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 erc7 erc6 erc5 erc4 erc3 erc2 erc1 erc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-35. external ra te correction register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved erca erce eoca eoce r r r r rw rwh rw rwh figure 3-36. external co rrection control register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 83 note if this bit is set by the host, external offset correction will be performed once during the subsequent double cycle; afte rwards, this bit will be cleared automatically by the communication controller. eoca ? external offset correction application 0 ? add external offset correction value. 1 ? subtract external offset correction value. erce ? external rate correction enable 0 ? external rate correction disabled. 1 ? external rate correction enabled. note if this bit is set by the host, the ex ternal rate correction will be performed once during the subsequent double cycle, and afterwards this bit will be automatically cleared by the communication controller. erca ? external rate correction application 0 ? add external rate correction. 1 ? subtract external rate correction. 3.2.3.3.24 maximum offset correction register (mocr) flexray protocol related parameter ? poffsetcorrectionout address 0xda reset undefined state this register defines the maximum pe rmitted absolute offset correction va lue, in microticks, to be applied by the internal clock synchronization algorithms. this register can be wr itten during the configuration state only. the value of this register does not effect the external clock correction value. 15 14 13 12 11 10 9 8 moc15 moc14 moc13 moc12 moc11 moc10 moc9 moc8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 moc7 moc6 moc5 moc4 moc3 moc2 moc1 moc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-37. maximum offset correction register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 84 freescale semiconductor 3.2.3.3.25 maximum rate co rrection register (mrcr) flexray protocol related parameter ? pratecorrectionout address 0xdc reset undefined state this register defines the maximum permitted absolute rate correction value, in microticks, to be applied by the internal clock synchronization algorithms. this register can be wr itten during the configuration state only. the value of this register does not effect the external clock correction value. 3.2.3.3.26 coldstart m aximum register (csmr) flexray protocol related parameter ? gcoldstartattempts address 0xc0 reset undefined state the value in this register determin es the maximum number of coldstart at tempts that a coldstarting startup node is allowed to make, when trying to start up the network without receivi ng a valid response from another node. after this numbe r of coldstart attempts, the cc falls b ack to the integration listen state and does not perform another coldstart at tempt, until the controller enters and leaves the configuration state again. if the register is programmed with the value ?0?, then the cc is not allowed to start communication. writing the coldstart maximum register is possible dur ing the configuration state only. the value of this register must be within the range [0:32767]. 15 14 13 12 11 10 9 8 mrc15 mrc14 mrc13 mrc12 mrc11 mrc10 mrc9 mrc8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 mrc7 mrc6 mrc5 mrc4 mrc3 mrc2 mrc1 mrc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-38. maximum rate correction register 15 14 13 12 11 10 9 8 cms15 cms14 cms13 cms12 cms11 cms10 cms9 cms8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 csm7 csm6 csm5 csm4 csm3 csm2 csm1 csm0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-39. coldstart maximum register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 85 3.2.3.3.27 transmit start se quence length register (tsslr) flexray protocol related parameter ? gdtsstransmitter/pdtssreceiver address 0xba reset undefined state the tsslr defines the length, in bits, of the tr ansmit start sequence on the physical layer. bits tsslt[0:7] (lsb) define th e nominal length of the transmit start sequence for transmission. bits tsslr[8:15] (msb) define maximum length of th e transmit start seque nce for reception. writing is possible only duri ng the configuration state. 3.2.3.3.28 network management v ector length regi ster (nmvlr) flexray protocol related parameter ? gnetworkmanagementvectorlength address 0x3e reset 0x0 this register defines the length, in byte s, of the network management vector (see section 3.2.3.4.6, ?global network management vector n register, n = [0:5] (gnmvnr) ?). writing is possible during the configuration state only. the value of this register must be within the range [0:12]. 15 14 13 12 11 10 9 8 tsslr7 tsslr6 tsslr5 tsslr4 tsslr3 tsslr2 tsslr1 tsslr0 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 tsslt7 tsslt6 tsslt5 tsslt4 tsslt3 tsslt2 tsslt1 tsslt0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-40. transmit start sequence length register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved nmvl3 nmvl2 nmvl1 nmvl0 r r r r rw* rw* rw* rw* figure 3-41. network management vector length register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 86 freescale semiconductor 3.2.3.3.29 sync frame register (syncfr) address 0x94 reset 0x0 this register contains the identifier of the sync frame to be transmitted. this regist er can be written during the configuration state only. there is no sync frame to transmit, if this register holds the value 0x0. a hard reset clears the register. sup ? startup this bit sets the startup frame indicator. it can be written in the configuration state only. 1 ? cc is a startup node and has its startup fram e indicator set. 0 ? cc is not a startup node. 3.2.3.3.30 sync frame he ader register (synchr) address 0x96 reset undefined state this register contains the header crc of the sync fr ame to be transmitted. this register can be written during the configuration state only. 15 14 13 12 11 10 9 8 sup reserved reserved reserved reserved syncf10 syncf9 syncf8 rw* r r r r rw* rw* rw* 76543210 syncf7 syncf6 syncf5 syncf4 syncf3 syncf2 syncf1 syncf0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-42. sync frame register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved syncrc10 syncrc9 syncrc8 rrrrrrw*rw*rw* 76543210 syncrc7 syncrc6 syncrc5 syncrc4 syncrc3 syncrc2 syncrc1 syncrc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-43. sync frame header register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 87 note the synchr value overwrites the header crc field of a transmit message buffer that: a) has the same frame id as the syncf[0:10] field of the syncfr (see section 3.2.3.3.29, ?sync frame register (syncfr) ?), and b) was selected by the cc for transmission as a sync message. 3.2.3.3.31 bus guardian tick register (bgtr) address 0xae reset undefined state this register defines the period length of the bus guardi an tick to be provided by the cc to the bus guardian. the value bgt[0:4], is expressed in multiples of the cc microtick. writing this register is possible only during the configuration state. the value of this register must be within the range [2:16]. 3.2.3.3.32 delay count er register (dcr) address 0x3c reset 0x0 this register specifies the configurable part of the de lay between the reset of th e config bit (host writing mcr0.config) and the point in time when the contro ller actually leaves th e configuration state (see section 3.9.2, ?configuration state ?). the delay is configurable in steps of eight microticks, i.e. the configured value * 8 = delay in microticks eqn. 3-6 the host may write this register only during the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved bgt4 bgt3 bgt2 bgt1 bgt0 r r r rw* rw* rw* rw* rw* figure 3-44. bus guardian tick register 15 14 13 12 11 10 9 8 dc15 dc14 dc13 dc12 dc11 dc10 dc9 dc8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-45. delay counter register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 88 freescale semiconductor 3.2.3.3.33 debug port co ntrol register (dbpcr) address 0x38 reset 0x0 this register controls the output f unctions of the bgt and ar m_bg pins of the contro ller as described in table 3-3 . bits cntrl[7:4] determine the functionality of the port bgt pin. bits cntrl[3:0] determine the f unctionality of the port arm_bg pin. refer to 3.10, ?debug port ? for a detailed description of the debug functions. note the output function controls of bgt and arm_bg pins are independent of each other. therefore, they may be set with equal or different values. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 cntrl7 cntrl6 cntrl5 cntrl4 cntrl3 cntrl2 cntrl1 cntrl0 rw rw rw rw rw rw rw rw figure 3-46. debug port control register table 3-3. encoding of debug port control fields cntrl[7:4] and cntrl[3:0] cntrl[7:4], cntrl[3:0] mode of the bgt , mode of the arm_bg signal 0 normal operation of bgt and arm_bg ? 1 protocol state change pcs 2 slot start in static segment sss 3 minislot start mss 4 rxd after glitch filter on channel a ragfa 5 dynamic slot start on channel a dssa 6 start of frame on channel a sfa 7 received syntactically correct an semantically valid frame indication on channel a rcfa 8 start of a communication cycle scc 9macrotick mts 10 start of offset correction soc 11 ? ? 12 rxd after glitch filter on channel b ragfb memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 89 3.2.3.3.34 start of offset correcti on cycle time register (socctr) flexray protocol related parameter ? goffsetcorrectionstart address 0xe0 reset undefined state this register defines the delay time (i n multiples of macroticks ) after which the offset correction will start. writing this register is possible only during the configuration state. note the time interval between the start ti me of the nit (see nitcr) and the start of offset correction time is used by the cc for clock correction calculations. the minimum interval th at must be ensure d during nitcr and socctr programming can be calculated from equation 3-7 : delaymin = ceil(500t + 110t*msfr)/nmlr) + 1 [nominal mt] eqn. 3-7 therefore, the socctr value must be: socctr >= nitcr + delaymin [nominal mt] eqn. 3-8 13 dynamic slot start on channel b dssb 14 start of frame on channel b sfb 15 received syntactically correct an semantically valid frame indication on channel b rcfb 15 14 13 12 11 10 9 8 reserved reserved socct13 socct1 2 socct11 socct10 socct9 socct8 r r rw* rw* rw* rw* rw* rw* 76543210 socct7 socct6 socct5 socct4 s occt3 socct2 socct1 socct0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-47. start of offset correction cycle time register table 3-3. encoding of debug port control fields cntrl[7:4] and cntrl[3:0] (continued) cntrl[7:4], cntrl[3:0] mode of the bgt , mode of the arm_bg signal mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 90 freescale semiconductor 3.2.3.3.35 idle detecti on length register (idlr) flexray protocol related param eter ? gddynamicslotidlephase address 0xaa reset undefined state this register defines the number of minislots used by the cc for checking the duration of the network idle time between two consecutive frames in the dynamic se gment. this includes the dynamic slot idle phase. writing this register is possible only during the configuration state. the value of idlr depends on the valu es of the bit duration register ( section 3.2.3.3.1, ?bit duration register (bdr) ) and the minislot length register ( section 3.2.3.3.12, ?minislot le ngth register (mslr) ). it can be calculated using equation 3-9 . idlr = ceil( (11 * bdr) / (nmlr * mslr) ). eqn. 3-9 the value in the register must be in the range [1:15]. 3.2.3.3.36 symbol window c ontrol register (swctrlr) address 0x84 reset 0x0 this register controls the transm ission of symbols in a symbol wi ndow of a communication cycle. the register may be modified during the conf iguration state and during normal operation. chb and cha determine whether a symbol will be tr ansmitted on channel b or channel a, respectively. 1 ? symbol transmission enabled. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved idl3 idl2 idl1 idl0 r r r r rw* rw* rw* rw* figure 3-48. idle detection length register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved chb cha reserved reserved reserved reserved reserved rrwrwrrrrr figure 3-49. symbol window control register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 91 0 ? symbol transmission disabled. 3.2.3.3.37 wakeup mechanism c ontrol register (wmctrlr) address 0x8a reset 0x0 this register controls the transmission of wakeup symbols. the register ma y be modified in the configuration state only. chb and cha determine whether a wakeup symbol wi ll be transmitted on channel b or channel a, respectively. 1 ? wakeup symbol transmission enabled. 0 ? wakeup symbol transmission disabled. cnt[4:0] determine the number of wakeup symbols to be transmitted. the c ontroller will transmit at least two wakeup symbols if wakeup symbol transmission is enabled. 3.2.3.3.38 wakeup symbol tx idle register (wustxir) flexray protocol related param eter ? gdwakeupsymboltxidle address 0xea reset 0x0 this register controls the duration of the idle pe riod of wakeup symbols. bits cnt[7:0] determine the duration of the idle period in bi t durations on the network. the regi ster may be modified in the configuration state only. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved chb cha cnt4 cnt3 cnt2 cnt1 cnt0 r rw* rw* rw* rw* rw* rw* rw* figure 3-50. wakeup mechanism control register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-51. wakeup symbol tx idle register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 92 freescale semiconductor 3.2.3.3.39 wakeup symbol tx low register (wustxlr) flexray protocol related param eter ? gdwakeupsymboltxlow address 0xec reset 0x0 this register controls the duration of the low perio d of wakeup symbols. bits cnt[5:0] determine the duration of the low period in bit dur ations on the network. the register may be modified only during the configuration state. 3.2.3.3.40 listen tim eout with noise lengt h register (lnlr) flexray protocol related parameter ? glistennoise address 0xd6 reset undefined state this register controls the duration of the listen timeout with noise. bi ts cnt[4:0] dete rmine the duration of the listen timeout as a number of communicati on cycles. the register may be modified in the configuration state only. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 r r rw* rw* rw* rw* rw* rw* figure 3-52. wakeup symbol tx low register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved cnt4 cnt3 cnt2 cnt1 cnt0 r r r rw* rw* rw* rw* rw* figure 3-53. listen timeout with noise length register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 93 3.2.3.4 status registers 3.2.3.4.1 protocol state register (psr) address 0x0c reset 0x0 this register is used to indicate the internal state of the cc. this register is read-only for the host. a hard reset clears the register. note refer to note 2 in section 3.2.3.5.7, ?slot status counter n register, n = [0:7] (sscnr) ? for information on the mfr4 200 slot status monitoring mechanisms. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved ps4 ps3 ps2 ps1 ps0 r r r rhrhrhrhrh figure 3-54. protocol state register table 3-4. cc state coding cc state code (decimal) slot status monitoring available configuration 0 no initialize schedule 1 no normal active operation 2 yes normal passive operation 3 yes integration consistency check 4 yes integration listen 5 no coldstart listen 21 no integration coldstart check 22 yes join coldstart 23 yes coldstart collision resolution 24 no coldstart consistency check 25 yes coldstart gap 26 no wakeup 11 no mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 94 freescale semiconductor 3.2.3.4.2 current cycle count er value regi ster (cccvr) flexray protocol rela ted parameter ? vcycle address 0x0a reset 0x0 this register provides the current cycle counter value (bits cccv[4:0]). the register is cleared by a hard reset or when leaving the configur ation state. if the maximum value is reached, the counter wraps around to zero and continues counting. the current cycle counter value is measured in communication cycles. 3.2.3.4.3 current macrotick c ounter value register (cmcvr) flexray protocol relat ed parameter ? vmacrotick address 0x08 reset 0x0 this register indicates the current cycle time in macrot icks (bits cmcv[13:0]. the register is cleared by a hard reset or when leaving the conf iguration state. the cc increments the register during the cycle, and clears it at the start of a new cycle. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved cccv5 cccv4 cccv3 cccv2 cccv1 cccv0 r r rh rh rh rh rh rh figure 3-55. current cycle counter value register 15 14 13 12 11 10 9 8 reserved reserved cmcv13 cmcv12 cmcv11 cmcv10 cmcv9 cmcv8 r r rh rh rh rh rh rh 76543210 cmcv7 cmcv6 cmcv5 cmcv4 cmcv3 cmcv2 cmcv1 cmcv0 rh rh rh rh rh rh rh rh figure 3-56. current macrotick counter value register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 95 3.2.3.4.4 offset correcti on value register (ocvr) flexray protocol related par ameter ? voffsetcorrection address 0x32c reset undefined state this read-only register indicates the offset correct ion value, in microticks, calculated by the clock synchronization algorithm (bef ore external offset correction and before value limitation), at the end of each communication cycle. data in this re gister is presented in 2?s complement form. the value in this register is valid after a communication cycl e start and until its ni t start. the cc modifies ocvr during the nit. 3.2.3.4.5 rate correction value register (rcvr) flexray protocol related par ameter ? vratecorrection address 0x32a reset undefined state this read-only register indicates the rate correcti on value, in microticks, calculated by the clock synchronization algorithm (before external rate corr ection and value limitation), at the end of each odd communication cycle. data in this regist er is presented in 2?s complement form. 15 14 13 12 11 10 9 8 ocv15 ocv14 ocv13 ocv12 ocv11 ocv10 ocv9 ocv8 rh rh rh rh rh rh rh rh 76543210 ocv7 ocv6 ocv5 ocv4 ocv3 ocv2 ocv1 ocv0 rh rh rh rh rh rh rh rh figure 3-57. offset correction value register 15 14 13 12 11 10 9 8 rcv15 rcv14 rcv13 rcv12 rcv11 rcv10 rcv9 rcv8 rh rh rh rh rh rh rh rh 76543210 rcv7 rcv6 rcv5 rcv4 rcv3 rcv2 rcv1 rcv0 rh rh rh rh rh rh rh rh figure 3-58. rate correction value register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 96 freescale semiconductor 3.2.3.4.6 global network management vector n register, n = [0:5] (gnmvnr) address gnmv0r=0x40, gnmv1r=0x42, gnmv2r=0x4 4, gnmv3r=0x46, gnmv4r=0x48, gnmv5r=0x4a, reset 0x0 these read-only registers hold th e global network management vect or. the length of the network management vector is configured by means of the nmvlr register (see section 3.2.3.3.28, ?network management vector length register (nmvlr) ?). the gnmvnr registers are cleared during a hard reset. note if the nmvlr register is programmed with a value less than 12, then the remaining bytes of the gn mvnr registers (which ar e not used for network management vector accumu lating) will remain 0?s. the global network management vector, as pr esented in the communication cycle x, is the or-combination of all network management vector s received in the communication cycle x-1. the controller ensures that the value read from gnmv0r is consistent. the mapping between the receive mess age buffer payload bytes and the gnmvnr registers is shown in table 3-5 . (see also section , ?receive, receive fifo, and transm it message buffers are accessible to the host mcu only through the active receive, active transmit, and active receive fifo buffers. ?.) 15 14 13 12 11 10 9 8 gnmv15 gnmv14 gnmv13 gnmv12 gnmv11 gnmv10 gnmv9 gnmv8 rh rh rh rh rh rh rh rh 76543210 gnmv7 gnmv6 gnmv5 gnmv4 gnmv3 gnmv2 gnmv1 gnmv0 rh rh rh rh rh rh rh rh figure 3-59. global network management vector n register, n = [0:5] table 3-5. mapping between receive message buffer payload bytes and gnmvnr registers gnmvnr byte nmvectorn gnmv0r msb nmvector1 lsb nmvector0 gnmv1r msb nmvector3 lsb nmvector2 ? gnmv5r msb nmvector11 lsb nmvector10 memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 97 3.2.3.4.7 symbol window status channel a register (swsar) address 0x86 reset 0x0 this register holds the symbol window status for cha nnel a. the symbol window status is the same as a regular slot status as described in section 3.3.3, ?message buffer slot status vector ?, with the addition of the symb flag. symb ? symbol this flag indicates the reception of a symbol in the symbol window. 0 ? no symbol received. 1 ? symbol received. txcon ? tx conflict this flag indicates transmission conf licts, i.e. indicates that a recep tion is ongoing when the controller starts transmission. this bit indicates conflicts during tran smission in a symbol window. 0 ? no transmission conflict detected 1 ? transmission conflict detected refer to section 3.3.3, ?message buffer slot status vector ? for a description of the other bits in this register. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved symb ch r r r r r r rh rh 76543210 vce syncf nullf supf serr cerr bviol txcon rh rh rh rh rh rh rh rh figure 3-60. symbol window status channel a register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 98 freescale semiconductor 3.2.3.4.8 symbol window status channel b register (swsbr) address 0x88 reset 0x0 this register holds the symbol window status for cha nnel b. the symbol window status is the same as a regular slot status as described in section 3.3.3, ?message buffer slot status vector ?, with the addition of the symb flag. symb ? symbol this flag indicates the reception of a symbol in the symbol window. 0 ? no symbol received. 1 ? symbol received. txcon ? tx conflict this flag indicates transmission conf licts, i.e. indicates that a recep tion is ongoing when the controller starts transmission. this bit indicates conflicts during tran smission in a symbol window. 0 ? no transmission conflict detected 1 ? transmission conflict detected refer to section 3.3.3, ?message buffer slot status vector ? for a description of the other bits in this register. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved symb ch r r r r r r rh rh 76543210 vce syncf nullf supf serr cerr bviol txcon rh rh rh rh rh rh rh rh figure 3-61. symbol window status channel b register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 99 3.2.3.4.9 bus guardian st atus register (bgsr) address 0x3a reset 0x0 this register holds the bus guardian status. bgrr ? bus guardian reset request request to the host to reset the bus guardian. 1 ? bg reset request. 0 ? no bg reset request. bgsme0 ? bus guardian schedule monitoring error indication for channel a indication of a bus guardian sche dule monitoring error on channel a. 1 ? bgsm error on channel a. 0 ? no bgsm error on channel a. bgsme1 ? bus guardian schedule monitoring error indication for channel b indication of a bus guardian sche dule monitoring error on channel b. 1 ? bgsm error on channel b. 0 ? no bgsm error on channel b. note if at least one of the bgsme bits is set, the bgs bit is set in the isr0 (see section 3.2.3.6.6, ?interrupt st atus register 0 (isr0) ?), and an interrupt is generated if enabled (see section 3.2.3.5.5, ?interrupt enable register 0 (ier0) ?). 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved rese rved reserved bgsme1 bgsme0 bgrr rrrrrrhrhrh figure 3-62. bus guardian status register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 100 freescale semiconductor 3.2.3.5 interrupt and error signa ling related control registers 3.2.3.5.1 startup interrupt enable register (sier) address 0x16 reset 0x0 this register holds the interrupt enable flags rela ted to the startup interr upt status register (see section 3.2.3.6.7, ?startup interrupt status register (sisr) ?). the sier register is cleared during a hard reset. cdstmie ? coldstart max interrupt enable 1 ? coldstart max interrupt enabled. 0 ? coldstart max interrupt disabled. plfie ? plausibility failed interrupt enable 1 ? plausibility failed interrupt enabled. 0 ? plausibility failed interrupt disabled. cdstpnie ? coldstart path normal interrupt enable 1 ? coldstart path normal interrupt enabled. 0 ? coldstart path normal interrupt disabled. cdstpnsie ? coldstart path noise interrupt enable 1 ? coldstart path noise interrupt enabled. 0 ? coldstart path noise interrupt disabled. cdstpnsie ? coldstart path noise interrupt enable 1 ? coldstart path noise interrupt enabled. 0 ? coldstart path noise interrupt disabled 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved cdstpnsie cdstpnie plfie cdstmie r r r r rw rw rw rw figure 3-63. startup interrupt enable register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 101 3.2.3.5.2 maximum odd cycles without clock correction fatal register (mocwcfr) flexray protocol related parameter ? gmaxwithoutclockcorrectionfatal address 0xcc reset undefined state this register holds the maximum number of odd co mmunication cycles (doubl e cycles) before a node enters the diagnosis stop state due to missi ng sync frame pairs (missing rate correction). the register can be written only in the configurati on state. if the ccfcv re gister value equals the mocwcfr register value, the cc will enter the ?red? error state (see section 3.2.3.6.5, ?error handling level register (ehlr) ?), and will signal this to the host by raising an interrupt. according to the protocol specification, the value of th is register lies in the range [1:15]; however, the current implementati on supports values in the range [1:32767]. 3.2.3.5.3 maximum odd cycles without cloc k correction passive register (mocwcpr) flexray protocol related parameter ? gmaxwithoutclockcorrectonpassive address 0xd8 reset undefined state this register holds the maximum number of odd co mmunication cycles (doubl e cycles) before a node enters the passive state due to missing s ync frame pairs (missing rate correction). the register can be written only in the configur ation state. if the ccfcr register value (see section 3.2.3.6.4, ?clock correction fa iled counter register (ccfcr) ?) equals the mo cwcpr register value, the cc will enter the ?yellow? error state (see section 3.2.3.6.5, ?error handling level register (ehlr) ?), and will signal this to the ho st by raising an interrupt. accord ing to the protocol specification, 15 14 13 12 11 10 9 8 mcwcf15 mcwcf14 mcwcf14 mcwcf14 mcwcf14 mcwcf14 mcwcf14 mcwcf14 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 mcwcf14 mcwcf14 mcwcf14 mcwcf 4 mcwcf3 mcwcf2 mcwcf1 mcwcf0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-64. maximum odd cycles without clock correction fatal register 15 14 13 12 11 10 9 8 mcwcp15 mcwcp14 mcwcp13 mcwcp12 mcwcp11 mcwcp10 mcwcp9 mcwcp8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 mcwcp7 mcwcp6 mcwcp5 mcwcp4 mcwcp3 mcwcp2 mcwcp1 mcwcp0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-65. maximum odd cycles wit hout clock correction passive register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 102 freescale semiconductor the value of this register lies in the range [1:15]; however, the current implementation supports values in the range [1:32767]. 3.2.3.5.4 channel status error counter n register, n = [0:1] (csecnr) address 0x2c, 0x2e reset 0x0 channel status error counters csec 0r and csec1r wrap around after they reach the maximum value. these registers are reset when leaving the configuration state. csec0r is assigned to channel a of the cc. csec1r is assigned to channel b of the cc. the controller generates a slot status vector for: every static slot dynamic slots during whic h the controller receiv es or transmits a frame symbol window network idle time on either channel the controller increments the corr esponding channel status error counter once if any slot status error bit (bits 0?3 of the slot st atus vector) is set. channel status error counter s are independent of other slot status monitoring mechanisms, i.e. message buffers ( section 3.2.3.7, ?message buffers and fifo configuration related registers ?), slot status registers ( section 3.2.3.6.8, ?slot status n re gister with n = [0:7] (ssnr) ?), and slot status counters ( section 3.2.3.5.7, ?slot status counte r n register, n = [0:7] (sscnr) ?). note to determine the number of errors th at occurred during a certain period of time, the host must store intermed iate values of the channel status error counters. if a frame exceeds a slot boundary, the controller increments the channel status error counter twice, becau se a slot boundary violation always affects two slots. 15 14 13 12 11 10 9 8 cnt15 cnt14 cnt13 cnt12 cnt11 cnt10 cnt9 cnt8 rh rh rh rh rh rh rh rh 76543210 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 rh rh rh rh rh rh rh rh figure 3-66. channel status error counter n register, n = [0:1] memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 103 refer to table 3-4 for slot status monitoring availability in different protocol states. 3.2.3.5.5 interrupt enab le register 0 (ier0) address 0x14 reset 0x0 each bit in the ier0 register enables its co rresponding interrupt in the isr0 register (see section 3.2.3.6.6, ?interrupt status register 0 (isr0) ?). their meaning is as follows: 0 ? the corresponding interrupt is disabled. 1 ? the corresponding interrupt enabled. 3.2.3.5.6 slot status selection n register, n = [0:3] (sssnr) address sss0r=0x6c, sss1r=0x 6e, sss2r=0x70, sss3r=0x72 reset 0x0 this set of n registers selects the st atic slot ids for which the status wi ll be provided in the ssnr registers (see section 3.2.3.6.8, ?slot status n register with n = [0:7] (ssnr) ?). note sssnr cannot be used for dynamic slots or minislots. id[0:10] ? slot status slot id selection id[0:10] select the id of the slot to observe. 15 14 13 12 11 10 9 8 fatalie cclrie maxsyncie ehlcie mrceie ssintie bgsie moceie rw rw rw rw rw rw rw rw 76543210 tif1ie tif0ie cycie rfoie rfneie chierrie txie rxie rw rw rw rw rw rw rw rw figure 3-67. interrupt enable register 0 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved id10 id9 id8 rrrrrrwrwrw 76543210 id7 id6 id5 id4 id3 id2 id1 id0 rw rw rw rw rw rw rw rw figure 3-68. slot status selection n register, n = [0:3] mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 104 freescale semiconductor 3.2.3.5.7 slot status counter n register, n = [0:7] (sscnr) address ssc0r=0x4c, ssc1r=0x4e, ssc2r=0x50, ss c3r=0x52, ssc4r=0x54, ss c5r=0x56, ssc6r=0x58, ssc7r=0x5a reset 0x0 slot status counters may trigger inte rrupts via the sscir register (see section 3.2.3.5.9, ?slot status counter incrementation register (sscir) ?). these interrupts may be enab led via the sscimr register (see section 3.2.3.5.10, ?slot status counter in terrupt mask register (sscimr) ?). refer to table 3-4 for slot status monitoring availability in differ ent protocol states. the controller increments the internal slot status counter when ever the slot status pr ovided by the protocol engine fulfills the status condition specified in th e corresponding slot status counter condition register ssccnr. the internal slot status c ounter is not directly vi sible to the host. depe nding on the value of bit multcyc of the correspondi ng register ssccnr (see section 3.2.3.5.8, ?slot stat us counter condition n register, n = [0:7] (ssccnr) ?), the controller either clears the in ternal slot status counter with every cycle start (multcyc = 0) or keeps on in crementing continuously (multcyc = 1). the host always gets the value of the internal slot status counter for the previous comunication cycle (multcyc = 0) or cycles (multcyc = 1), when accessing slot status counters sscnr. slot status counters do not wraparound. note 1 to clear slot status counter sscnr , the host must reset bit multcyc in the corresponding slot status c ounter condition regi ster ssccnr. the controller will then reset the internal slot status counter at the beginning of the following cycle, and the host wi ll get the accumulated value of the internal slot status counter at the end of the following cycle. the controller clears all internal sl ot status counters when leaving the configuration state. the controller clears an internal slot status counter at the beginning of every cycle, if bit multcyc is 0 in the corresponding slot status counter condition register. note 2 the controller provides four inde pendent slot status monitoring mechanisms: 15 14 13 12 11 10 9 8 cnt15 cnt14 cnt13 cnt12 cnt11 cnt10 cnt9 cnt8 rh rh rh rh rh rh rh rh 76543210 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 rh rh rh rh rh rh rh rh figure 3-69. slot status counter n register, n = [0:7] memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 105 slot status registers ssnr configured via slot status selection registers sssnr, as described in section 3.2.3.6.8, ?slot status n register with n = [0:7] (ssnr) ? and section 3.2.3.5.6, ?slot status selection n register, n = [0:3] (sssnr) ?. channel status error counters csec0r and csec1r, as described in section 3.2.3.5.4, ?channel status erro r counter n register, n = [0:1] (csecnr) ?. slot status information within me ssage buffers, as described in section 3.3.3, ?message buffer slot status vector ?. slot status counter registers sscnr configured via slot status counter condition registers ss ccnr as described in section 3.2.3.5.7, ?slot status counter n register, n = [0:7] (sscnr) ? and section 3.2.3.5.8, ?slot status counter condition n register, n = [0:7] (ssccnr) ?. refer to table 3-4 for slot status monitoring availability in different protocol states. 3.2.3.5.8 slot status counter cond ition n register, n = [0:7] (ssccnr) address sscc0r=0x5c, sscc1r=0x5e, sscc2r=0x60, ss cc3r=0x62, sscc4r=0x64, sscc5r=0x66, sscc6r=0x68, sscc7r=0x6a reset 0x0 each of these registers serves as condition to detect if the corresponding slot status counter (see section 3.2.3.5.7, ?slot status counter n register, n = [0:7] (sscnr) ?) is to be incremented. sscmx, x = [0:3] ? slot status mask a binary and operation is pe rformed on this 4-bit vector and the stat us of each slot-cha nnel tuple that is not booked for transmission in the st atic part of the communication cycle. if the result is 0, and conditions for null frame sele ction (nulls), sync frame selection (syncs), startup frame selection (supfs), and valid co mmunication elemen t selection (vces) are no t met, the counter will not be incremented for that slot-channel tuple. nullfs ? null frame selection this register is used to restrict counting to received null frames only. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved chcfg1 chcfg0 multcyc rrrrrrwrwrw 76543210 vces syncfs nullfs supfs sscm3 sscm2 sscm1 sscm0 rw rw rw rw rw rw rw rw figure 3-70. slot status counter condition n register, n = [0:7] mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 106 freescale semiconductor 0 ? the slot status counter is incremented independently of the nul l frame indication bit. 1 ? the slot status counter is incremented only wh en a syntactically correc t null frame is received. syncfs ? sync frame selection this register can be used to restrict counting to received sync frames only. 0 ? the slot status counter can be increm ented independently of the sync frame bit. 1 ? the slot status counter can be incremented only wh en a syntactically correct sync frame is received. supfs ? startup frame selection this register can be used to restrict counting to receive d startup frames only. 0 ? the slot status counter can be incr emented independently of the startup bit. 1 ? the slot status counter can be incremented only when a syntactically correct st artup frame is received. vces ? valid communication element selection this register can be used to restrict counting to semantical ly valid frames only. 0 ? the slot status counter can be incremen ted for semantically va lid and invalid frames. 1 ? the slot status counter can be incremented only when a semantically valid frame is received. multcyc ? multiple cycle this bit determines if the slot status counter reflects the values of mult iple communication cycles or of the previous communication cycle only. note that multcyc may be writt en during normal operation, but its value must not be modified by the host during the nit. 0 ? the internal slot status counte r starts at 0 at the beginning of every communication cycle, and sscnr reflects the values of the previous communication cycle. 1 ? the internal slot status counter is not reset to 0 at the beginning of every communication cycle; this allows counting of specific slot status conditions over several comm unication cycles. sscnr reflects the accumulated values counted in previous communication cycles. chcfg1, chcfg0 ? channel configuration these bits determine the channel assignment fo r slot status counters sscnr, as defined in table 3-6 . table 3-6. channel configuration for ssccnr chcfg1 chcfg0 meaning 0 0 count for channel a 0 1 count for channel b memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 107 note slot status counting is supporte d for the static segment only. 3.2.3.5.9 slot status counter in crementation register (sscir) address 0x28 reset 0x0 this register contains one bit, sscirn, for each slot status counter sscnr (see section 3.2.3.5.7, ?slot status counter n register, n = [0:7] (sscnr) ?). bit sscirn is set when the slot status c ounter sscnr is incremented. the register is reset on leaving the configuration state. the host may clear individually each bit in register sscir by writing a ?1? to it. 3.2.3.5.10 slot status counter interrupt mask register (sscimr) address 0x2a reset 0x0 1 0 count for both channels only once even if the counting condition is fulfilled for both channels 1 1 count for both channels independently. if the counting condition is fulfilled for both channels, count twice. 15 14 13 12 11 10 9 8 00000000 rrrrrrrr 76543210 sscir7 sscir6 sscir5 sscir4 sscir3 sscir2 sscir1 sscir0 rwh rwh rwh rwh rwh rwh rwh rwh figure 3-71. slot status counter incrementation register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 sscimr7 sscimr6 sscimr5 sscimr4 sscimr3 sscimr2 sscimr1 sscimr0 rw rw rw rw rw rw rw rw figure 3-72. slot status counter interrupt mask register table 3-6. channel configuration for ssccnr chcfg1 chcfg0 meaning mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 108 freescale semiconductor via this register, the host may enable in dividually each bit in the sscir (see section 3.2.3.5.9, ?slot status counter incrementation register (sscir) ?) to trigger the interrupt ssint in the isr0 (see section 3.2.3.6.6, ?interrupt st atus register 0 (isr0) ?. 1 ? if the corresponding bit in register sscir is set, trigger the interrupt ssint. 0 ? ignore the corresponding bit in register sscir; do not trigger an interrupt. 3.2.3.6 interrupt and error signa ling related status registers 3.2.3.6.1 receive buffer interrup t vector register (rbivecr) address 0x24 reset 0x0 this register indicates the lowest num bered receive message buff er that has its interrupt status flag (iflg) and its interrupt enable (iena) bits set. the regist er is cleared by a hard reset or by leaving the configuration state. note after an iflg has been set or cleared, the cc updates the rbivecr register after 1 t. the rbivecr register contains valid data only if the rxif bit is set (see section 3.2.3.6.6, ?interrupt status register 0 (isr0) ?). if there are no iflg bits set for an y receive message buffers that have their iena bit set, then the cc sets the rbivecr register to 0x0000 (iflg, iena ? see section 3.2.3.7.2, ?message buffer control, configuration and status n register, n = [0:58] (bufcsnr) ?). 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved rbivec5 rbive c4 rbivec3 rbivec2 rbivec1 rbivec0 r r rh rh rh rh rh rh figure 3-73. receive buffer interrupt vector register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 109 3.2.3.6.2 transmit buffer interr upt vector regi ster (tbivecr) address 0x26 reset 0x0 this register indicates the lowest numbered transmit me ssage buffer that ha s its interrupt st atus flag (iflg) and its interrupt enable (iena) bits set. a hard reset or leaving the configuration state clear the register. note after an iflg has been set or cleared, the cc updates the tbivecr register after 1 t. the tbivecr register contains valid data only if the txif bit is set (see section 3.2.3.6.6, ?interrupt st atus register 0 (isr0) ?). if there are no iflg bits set for any transmit me ssage buffers that have their iena bit set, then the cc sets the tbivecr register to 0x0000 (iflg, iena ? see section 3.2.3.7.2, ?message buffer control, configuration and status n register, n = [0:58] (bufcsnr) ?). 3.2.3.6.3 chi erro r register (chier) address 0x12 reset 0x0 this register holds chi status flag s. the host clears any status bit in the chier by writing a '1' to it; writing a ?0? does not change the bit st ate. the cc sets a stat us bit in the chier agai n, when it detects the condition for that bit. if the host and the cc try to write the chier regist er at the same time, the cc write 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved tbivec5 tbivec4 tbivec3 tbivec2 tbivec1 tbivec0 r r rh rh rh rh rh rh figure 3-74. transmit buffer interrupt vector register 15 14 13 12 11 10 9 8 illadr nmenf nmefts splme mdple bule efle fble rwh rwh rwh rwh rwh rwh rwh rwh 76543210 tble rble reserved ccpble bb reserved ire fle rwh rwh r rwh rwh r rwh rwh figure 3-75. chi error register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 110 freescale semiconductor operation has the higher priority. if th e host tries to clear a set error flag in the chier register, while the cc at the same time sets this bit, the error flag wi ll remain set. a hard reset clears the register. note when any error is processed by the cc , and indicated in the chier register, the cc raises an interrupt, if configured to do so by means of the isr0 and ier0 bits, and continues ope ration without changing state. fle ? frame lost error this error occurs if the host has locked a receive message buffer, and two semant ically valid frames for that buffer are received during this locked time. the first frame will be lost. 1 ? frame lost error detected. 0 ? no frame lost error detected. ire ? illegal reconfiguration error this error appears if the host tries to reconfigure a dynamic transmit message buffer to a static one. the reconfiguration, in that case , is ignored by the cc. 1 ? illegal reconfiguration error detected. 0 ? no illegal reconfiguration error detected. bb ? buffer busy this bit is set if the host tr ies to lock a message buffer that is locked by the cc for internal operations. the cc, in that case, does not grant access to the message buffer through the locking mechanism. 1 ? buffer busy detected. 0 ? no buffer busy detected. buffer locking errors: ccpble ? cc part buffer of a double transmit message buffer lock error this error is raised if the host tries to lock a cc pa rt buffer of a double transmit message buffer. the cc, in that case, does not grant access to the cc part buffer of a double transmit message buffer through the locking mechanism. 1 ? ccpble detected. 0 ? no ccpble detected. rble ? receive message buffers locking error this error appears if the host tries to lock more th an 1 receive message buffer. the cc in that case does not grant access to the buffer through the locking mechanism. 1 ? rble detected. memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 111 0 ? no rble detected. tble ? transmit message buffers locking error this error appears if the host tries to lock more than one transmit me ssage buffer. the cc, in that case, does not grant access to the buffer through the locking mechanism. 1 ? tble detected. 0 ? no tble detected. fble ? fifo message buffer lock error this error appears if the host tries to lock a fifo message buffer not through message buffer 0. the cc, in that case, does not grant access to the m essage buffer through the locking mechanism. 1 ? fble detected. 0 ? no fble detected. efle ? empty fifo lock error this error appears if the host tries to lock an empt y fifo. the cc, in that ca se, does not grant access to the fifo through the locking mechanism. 1 ? efle detected. 0 ? no efle detected. bule ? unlocked message buffer lock error this error appears if the host trie s to access an unlocked m essage buffer through any active message buffer. in that case, the host write operations to an active message buffer are ignored, and read operations return 0?s. 1 ? bule detected. 0 ? no bule detected. other error indicators: mdple ? maximum dynamic payload length exceeded error this error appears if the payload length writte n into a dynamic segment transmit message buffer payloadlength field is greater than the maximum payloa d length dynamic configured in the maximum payload length dynamic register mpldr (see section 3.2.3.3.16, ?maximum payload length dynamic register (mpldr) ?). in that case, the wrong payload length is ignored. 1 ? mdple detected. 0 ? no mdple detected. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 112 freescale semiconductor splme ? static payload length mismatch error this error appears if the payload length written into a static segment transmit me ssage buffer is not equal to the static payload length configured within the static payload length register splr (see section 3.2.3.3.11, ?static payload length register (splr) ?). in that case, the wrong payload length is ignored. 1 ? splme detected. 0 ? no splme detected. nmefts ? network management error frame too short this error appears if the payload length value of a received message is not big enough to hold the complete configured nm vector. however, the received part of the nm vector is used for the nm vector update (see section 3.2.3.4.6, ?global network management vector n register, n = [0:5] (gnmvnr) ?). 1 ? nmefts detected. 0 ? no nmefts detected. nmenf ? network management error null frame this error appears if a received messa ge with an nm bit set has a null frame bit set. in that case, the gnmvnr registers are not updated. 1 ? nmenf detected. 0?no nmenf detected. illadr ? illegal address this error appears if the host tries to perform a by te access (a write access, if the hcs12 interface is selected) or an unaligned word access. if the hcs12 interface is selected (see chapter section 3.7, ?host controller interfaces ?), and this error appears, the cc presents the data value 0x0000 to the host and indicates an iiladr error. note the address space from 0x0400 to 0x1fff in the mfr4200 memory map is reserved. reading this address space results in data 0x0000, while writing does not change the memory. reading or writing this addr ess space will set the illadr bit. 1 ? illadr detected. 0 ? no illadr detected. memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 113 3.2.3.6.4 clock correction fail ed counter regi ster (ccfcr) flexray protocol related parameter ? vclockcorrectionfailed address 0x326 reset undefined state this register holds the clock correction failed count er. this counter is reset when a node enters normal active operation. it is incremented by one at the end of any odd communication cycle, when either the missing offset correction e rror or the missing rate corre ction error, or both, are ac tive. the counter is reset to zero at the end of an odd communication cycle if ne ither the offset correction failed error nor the rate correction failed error is active. the counter is not incremented after it reaches the maximum odd communication cycles w ithout clock correction programmed value (see section 3.2.3.5.2, ?maximum odd cycles without clock correct ion fatal register (mocwcfr) ?). the host has read-only access to this register. 3.2.3.6.5 error handling level register (ehlr) address 0x328 reset undefined state this register holds the current value of the error handling level. error handling levels are defined in table 3-7 : 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved owcc3 owcc2 owcc1 owcc0 r r r r rh rh rh rh figure 3-76. clock correction failed counter register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved rese rved reserved reserved ehl1 ehl0 r r r r r r rh rh figure 3-77. error handling level register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 114 freescale semiconductor 3.2.3.6.6 interrupt st atus register 0 (isr0) address 0x0e reset 0x0 this register indicates the occurrence of interrupt events. together with ier0 (see section 3.2.3.5.5, ?interrupt enable register 0 (ier0) ?), it allows the module to operate in a polled or interrupt driven system. note the host clears any status bit in the isr0 by writing a '1' to the bit. writing a ?0? does not change the bit state. the cc sets a status bit of the is r0 again when it detects the condition for that bit. the host must resolve the conditi ons causing the rfneif, chierrif, txif, and rxif bits to be asser ted, as these flags are updated automatically by the cc, depending on conditions related to these flags. if the host does not resolve the conditi ons that lead to these flags being asserted, the cc ignores the host?s cl ear operation for these bits and the bits remain asserted. if the host and the cc try to write the isr0 register at the same time, the cc operation has th e higher priority. every flag has an associated interrupt enable flag in interrupt enable regi ster 0. the isr0 re gister is cleared by a hard reset or by leaving the configuration state. table 3-7. error handling level coding ehl1 ehl0 error handling level cc state 0 0 green level normal active 0 1 yellow level normal passive 1 0 red level diagnosis stop 11 not used ? 15 14 13 12 11 10 9 8 fatal cclr maxsync ehlc mrce ssint bgs moce rwh rwh rwh rwh rwh rwh rwh rwh 76543210 tif1 tif0 cycif rfoif rfneif chierrif txif rxif rwh rwh rwh rwh rwh rwh rwh rwh figure 3-78. interrupt status register 0 memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 115 rxif ? receive interrupt flag this bit is set when any of the enabled (ienan = 1) receive message buffers or the receive fifo has successfully received a frame. sources of th is interrupt are set iflg bits (see section 3.4.1, ?message buffer control, configur ation and status register ?) of the correspondi ng message buffers. if rxie is set (see section 3.2.3.5.5, ?interrupt enable register 0 (ier0) ?), a receive interrupt remains pending while the rxif flag is set. 1 ? at least one receive m essage buffer is full. 0 ? all receive message buffers are empty. txif ? transmit interrupt flag this read-only bit is set when any of the enable d (ienan = 1) transmit message buffers is empty (iflg = 1). sources of this interrupt are set iflg bits (see section 3.4.1, ?message buffer control, configuration and status register ?) of the corresponding message bu ffers. if txie is set (see section 3.2.3.5.5, ?interrupt enable register 0 (ier0) ?), an interrupt remains pendi ng while this flag is set. 1 ? at least one transmit message buffer is empty. 0 ? all transmit message buffers are full. chierrif ? chi error interrupt flag this bit is set when a chi error is detected. sources of this interrupt ar e chi errors in the chier register (see section 3.2.3.6.3, ?chi erro r register (chier) ?). if chierrif is set, an interrupt remains pending while this flag is set. 1 ? a chi error was detected. 0 ? no chi error was detected. rfneif ? receive fifo not empty interrupt flag this bit is set when the receive fi fo is not empty. if enabled, a fifo not empty interrupt remains pending while this flag is set. the flag wi ll be cleared if the fi fo is empty and message buffer 0 is unlocked. the cc sets this flag when the fifo is not empty. 1 ? receive fifo is not empty. 0 ? receive fifo is empty. rfoif ? receive fifo overrun interrupt flag this bit is set when a receive fifo overrun occurs. if enabled, an interrupt rema ins pending while this flag is set. 1 ? a receive fifo overrun has been detected. 0 ? no receive fifo overrun has occurred. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 116 freescale semiconductor cycif ? cycle start interrupt flag this bit is set when a co mmunication cycle starts. if enabled, an interrupt remain s pending while this flag is set. 1 ? a communication cycle started. 0 ? no communication cycle started. tif0/tif1 ? timer interrupt flag 0/1 this bit is set when: the result of the timer 0/1 interrupt calculation, based on the cycle base and repetition fields of the timer interrupt configuration register 0 (see section 3.2.3.9.1, ?timer interrupt configuration register 0 cycle set (ticr0cs) ?), matches the current cycle count er value in the cccv register (see section 3.2.3.4.2, ?current cycle counter value register (cccvr) ?); and the macrotick offset progr ammed in the timer interrupt co nfiguration register 0 (see section 3.2.3.9.1, ?timer interrupt configurat ion register 0 cycle set (ticr0cs) ?) matches the current macrotick value from cmcvr (see section 3.2.3.4.3, ?current macrotick counter value register (cmcvr) ?). if enabled, an interrupt remains pending while this flag is set. 1 ? timer 0/1 has reached the limit. 0 ? timer 0/1 has not reached the limit. note after a hard reset, timer interrupt c onfiguration registers are cleared. the cc indicates timers interrupts (isr0 = 0x00c0) immediately after the hard reset, as the protocol engine provides cycle time and cycle counter values equal to zero during the whole configura tion state. no interrupt is indicated to the host, as the interrupt enable regi ster ier0 is also 0 after a hard reset. moce ? missing offset correction error this bit is set if an insufficient num ber of measurements is available for offset correction at the end of the communication cycle (even and odd). 1 ? insufficient number of measuremen ts available for offset correction. 0 ? sufficient number of measurement s available for offset correction bgs ? bus guardian status this bit indicates bus guardian sc hedule monitoring errors on channel a and/or channel b. the host may read the bus guardian stat us register bgsr (see section 3.2.3.4.9, ?bus guardian status register (bgsr) ?) to determine on which channel the error occu rred. the host may reset bgs by writing a ?1?. 1 ? bus guardian schedul e monitoring error. 0 ? no bus guardian schedule monitoring error memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 117 ssint ? slot status interrupt this bit indicates that at least one sl ot status counter register sscnr (see section 3.2.3.5.7, ?slot status counter n register, n = [0:7] (sscnr) ?) that is enabled as an interrupt source via slot status counter interrupt mask register sscimr (see section 3.2.3.5.10, ?slot status counter interrupt mask register (sscimr) ?) has been incremented. 1 ? at least one slot status count er that is enabled as an interr upt source has been incremented. 0 ? no slot status counter that is enable d as an interrupt source has been incremented. mrce ? missing rate correction error this bit is set if an insufficient number of measurement pairs is available for rate correction at the end of the odd communication cycle. 1 ? insufficient number of measuremen t pairs available for rate correction 0 ? sufficient number of measurement pairs available for rate correction ehlc ? error handling level changed/ startup interrupt detected this signal indicates, to the host, changes to the error handling level. 1 ? error handling level has changed. 0 ? error handling level has not changed. maxsync ? max sync frames detected the controller sets this bit when more than the configured maximum num ber of sync frames (see section 3.2.3.3.5, ?maximum sync frames register (msfr) ?) are detected within a single cycle. in this case, the controller is not able to cap ture all time difference measurements. 1 ? more than the configured maximum number of sync frames have been received. 0 ? not more than the configured maximum number of sync frames have been received. cclr ? clock correction limit reached this bit is set if offset or rate calculation reach es the threshold as configured in registers mocr and mrcr (see section 3.2.3.3.24, ?maximum offset correction register (mocr) ? and section 3.2.3.3.25, ?maximum rate correct ion register (mrcr) ?). 1 ? offset or rate calculation has reached the limit. 0 ? offset and rate correct ion are within the limit. fatal ? fatal error this bit is set if an illegal condition is detected in the protoc ol state machine; this can be caused by illegal configuration. in this as, the controller goe s into the diagnosis stop state immediately. 1 ? fatal error detected. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 118 freescale semiconductor 0 ? no fatal error detected. 3.2.3.6.7 startup interrupt status register (sisr) address 0x10 reset 0x0 this register holds the interrupt flags related to the st artup procedure. all flags ar e read/write for the host. each flag has an associated interrupt enable flag in the startup interrupt enable register (see section 3.2.3.5.1, ?startup interrupt enable register (sier) ?). the sisr register is cleared during a hard reset or when leaving the configuration state. the host clears a status bit in the sisr by writing a '1' to it. writing a ?0? does not change the bit state. the cc sets a status bit in the sisr agai n when it detects the condition for that bit. if the host and the cc try to access the sisr register at the same ti me, the cc operation has the higher priority. cdstmif ? coldstart max interrupt flag this error signal is set if the maximum number of allowed retries of a coldstarting cc (csmr programmed value ? see section 3.2.3.3.26, ?coldstart ma ximum register (csmr) ?) is reached. that is, if the csmr register is programme d with the value n, the cc sets the cdstmif bit after the nth retry has failed. if enabled, an interrupt re mains pending while this flag is set. 1 ? coldstart maximum value has been reached. 0 ? coldstart maximum value has not been reached. plfif ? plausibility failed interrupt flag this error signal is set if the consistency check of the local cc within the start up sequence failed, i.e. the number of received valid startup frames is less than required. if enabled, an interrupt remains pending while this flag is set. 1 ? a plausibility check of the local cc within the startup sequence failed. 0 ? a plausibility check of the local cc within the startup sequence did not fail. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved cdstpnsif cdstpnif plfif cdstmif r r r r rwh rwh rwh rwh figure 3-79. startup interrupt status register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 119 cdstpnsif ? coldstart path noise interrupt flag this signal is set if the cc has ente red startup via the coldstart noise pat h. this indicates that the cc tried to start the network. if enabled, an interr upt remains pending while this flag is set. 1 ? the startup has been entered via the coldstart noise path. 0 ? the startup has not been ente red via the coldstart noise path. cdstpnif ? coldstart path normal interrupt flag this signal is set if the cc has entered the startup vi a the normal coldstart path. this indicates that the cc tried to start the network. if enabled, an in terrupt is pending whil e this flag is set. 1 ? startup has been entered via the normal coldstart path. 0 ? startup has not been entered via the normal coldstart path. 3.2.3.6.8 slot status n regi ster with n = [0:7] (ssnr) address ss0r=0x74, ss1r=0x76, ss2r=0x78, ss3r=0x 7a, ss4r=0x7c, ss5r=0x7e, ss6r=0x80, ss7r=0x82 reset 0x0 each of these registers holds the status of the slot specified in the corres ponding slot status selection register sssnr for both channel a and channel b. the suffices ?_a? and ?_b? indicate whether the slot status is valid for channel a or channel b, respectively . for a detailed description of the slot status flags, refer to section 3.3.3, ?message buffer slot status vector ?. the controller provides a pair of sl ot status registers for each monitore d slot with the first register being assigned to even communication cycles, and the second to odd comm unication cycles, as shown in table 3-8 . the controller clears the slot status registers ssnr (see section 3.2.3.6.8, ?slot status n register with n = [0:7] (ssnr) ?) when leaving the configuration state. note refer to table 3-4 for slot status monitoring availability in different protocol states. the slot status of slot n is updated within the f irst macrotick of slot n+1. 15 14 13 12 11 10 9 8 vce_b syncf_b nullf_b supf_b ser r_b cerr_b bviol_b txcon_b rh rh rh rh rh rh rh rh 76543210 vce_a syncf_a nullf_a supf_a ser r_a cerr_a bviol_a txcon_a rh rh rh rh rh rh rh rh figure 3-80. slot status n register, n = [0:7] mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 120 freescale semiconductor empty slots exhibit the slot status 0x00 for both channels, because the slot status registers ssnr do not in clude the slot status channel bit. 3.2.3.6.9 odd sync frame id n register, n = [0:15] (osfidnr) address osfid0r=0x3e0 ? osfid15r=0x3fe reset undefined state these registers hold the frame ids of all sync frames received in odd communication cycles and used for clock synchronization. the cc does not change the odd id va lues from the end of th e static part in the odd cycle to the beginning of the nit in the even communication cycle. note if a cc is configured to send sync frames (see section 3.2.3.3.29, ?sync frame register (syncfr) ?), the cc will store its s ync frame id in register osfid0r. table 3-8. mapping between sssnr and ssnr slot status selection register even communication cycle o dd communication cycle channel a (low byte) channel b (high byte) channel a (low byte) channel b (high byte) sss0r ss0r ss0r ss1r ss1r sss1r ss2r ss2r ss3r ss3r sss2r ss4r ss4r ss5r ss5r sss3r ss6r ss6r ss7r ss7r 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved id10 id9 id8 rrrrrrhrhrh 76543210 id7 id6 id5 id4 id3 id2 id1 id0 rh rh rh rh rh rh rh rh figure 3-81. odd sync frame id n register, n = [0:15] memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 121 3.2.3.6.10 even sync frame id n register, n = [0:15] (esfidnr) address eid0r=0x380 ? eid15r=0x39e reset undefined state these registers hold the slot ids of all sync frames received in even communication cycles and used for clock synchronization. the cc does not ch ange the even id values from th e end of the static part in the even cycle to the beginning of th e nit in the odd communication cycle. note if a cc is configured to send sync frames (see section 3.2.3.3.29, ?sync frame register (syncfr) ), each time the cc cl ears the emcr or omcr, it: initializes the esfid0r (or osfi d0r) with its sync frame id, increments emcr or omcr, initializes ema0r and emb0r or oma0r and emb0r with the following value: nmlr * ssapor ? tsslr * bdr ? max(dcar,dcbr) ? 4 eqn. 3-10 3.2.3.6.11 odd measurem ent channel a n regist er, n = [0:15] (omanr) address oma0r=0x3a0 ? oma15r=0x3be reset undefined state 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved id10 id9 id8 rrrrrrhrhrh 76543210 id7 id6 id5 id4 id3 id2 id1 id0 rh rh rh rh rh rh rh rh figure 3-82. even sync frame id n register, n = [0:15] 15 14 13 12 11 10 9 8 oma15 oma14 oma13 oma12 oma11 oma10 oma9 oma8 rh rh rh rh rh rh rh rh 76543210 oma7 oma6 oma5 oma4 oma3 oma2 oma1 oma0 rh rh rh rh rh rh rh rh figure 3-83. odd measurement channel a n register, n = [0:15] mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 122 freescale semiconductor these registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. registers oma0r to oma15r contain all measu rement values from channel a for the odd communication cycle. 3.2.3.6.12 odd measurem ent channel b n regist er, n = 0:15] (ombnr) address omb0r=0x3c0 ? omb15r=0x3de reset undefined state these registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. registers omb0r to omb15r contain all m easurement values from channel b for the odd communication cycle. 3.2.3.6.13 even measurem ent channel a n regist er, n = [0:15] (emanr) address ema0r=0x340 ? ema15r=0x35e reset undefined state these registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. registers ema[0:15]r contain all measurement values from channel a for the even communication cycle. 15 14 13 12 11 10 9 8 omb15 omb14 omb13 omb12 omb11 omb10 omb9 omb8 rh rh rh rh rh rh rh rh 76543210 omb7 omb6 omb5 omb4 omb3 omb2 omb1 omb0 rh rh rh rh rh rh rh rh figure 3-84. odd measurement channel b n register, n = [0:15] 15 14 13 12 11 10 9 8 ema15 ema14 ema13 ema12 ema11 ema10 ema9 ema8 rh rh rh rh rh rh rh rh 76543210 ema7 ema6 ema5 ema4 ema3 ema2 ema1 ema0 rh rh rh rh rh rh rh rh figure 3-85. even measurement channel a n register, n = [0:15] memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 123 3.2.3.6.14 even measurem ent channel b n regist er, n = [0:15] (embnr) address emb0r=0x360 ? emb15r=0x37e reset undefined state these registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. registers emb[0:15]r contain all m easurement values from channel b for the even communication cycle. note to get the time difference based on the expected time reference point, one must subtract the nominal action point offset in mi croticks, the frame start sequence length and the delay compensation according to the formula below: time difference = (emanr, embnr, omanr, or ombnr) ? nmlr * ssapor ? tsslr * bdr ? max(dcar,dcbr) ? 4 eqn. 3-11 as the transmission start sequence length is given in bits , it must be converted to t by multiplying it by the bit duration. as the channel informat ion is not available for the list of sync frame arrival times, the cc standardizes the values based on the channel with the larger delay compensation value; thereby, the frame arrival time is always positive. a sync frame arrival time of 0 in one of the measurement registers denot es an invalid time difference. for example, if, in a given slot, onl y a sync frame on channel a has b een received, the corresponding embnr will hold the value 0. 15 14 13 12 11 10 9 8 emb15 emb14 emb13 emb12 emb11 emb10 emb9 emb8 rh rh rh rh rh rh rh rh 76543210 emb7 emb6 emb5 emb4 emb3 emb2 emb1 emb0 rh rh rh rh rh rh rh rh figure 3-86. even measurement channel b n register, n = [0:15] mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 124 freescale semiconductor 3.2.3.6.15 even measurement counter regi ster (emcr) address 0x33c reset undefined state the emcr and omcr are described in the following section. 3.2.3.6.16 odd measurement counter register (omcr) address 0x33e reset undefined state the emcr and omcr hol d the number of valid sync frames received during the st atic segment of an even or odd cycle, respectively. if sync frame filtering is enabled, only sync fr ames that have passed the sync frame rejection and/or acceptance filters (see section 3.2.3.8.3, ?sync frame re jection filter register (synfrfr) ? and section 3.2.3.8.1, ?sync frame acceptance filter value register (synfafvr) ?) are considered. the emcr and omcr re gisters hold the number of valid measurements in the measurement tables (see section 3.2.3.6.9, ?odd sync frame id n register, n = [0:15] (osfidnr) ? and section 3.2.3.6.11, ?odd measureme nt channel a n register, n = [0:15] (omanr) ?). for example, if the value of emcr is two, then two valid sync frames are available for clock sync ca lculations; the remaining fourteen values in the measurement table for the ev en cycle are invalid and may have undefined content. the emcr and omcr counters are incremented each ti me, when a valid sync frame has been received on at least one of the channels. emcr and omcr are reset when the cc enters the initialize schedule and coldstart collision resolution states. in the normal active state a nd the normal passive state, emcr is r eset in the nit of the odd cycle, and omcr is reset at the end of the even cycle. if the node is a non sync node, emcr and omcr are 15 14 13 12 11 10 9 8 reserved reserved reserved reserved re served reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved emc3 emc2 emc1 emc0 r r r r rh rh rh rh figure 3-87. even measurement counter register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved re served reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved omc3 omc2 omc1 omc0 r r r r rh rh rh rh figure 3-88. odd measurement counter register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 125 reset to zero. if the node is a sync node, emcr and omcr are reset to 1, as a sync node considers its own sync frames as zero values in the measurement tables. 3.2.3.7 message buffers and fifo configuration related registers 3.2.3.7.1 fifo size register (fsizr) address 0x18 reset 0x0 this register is used to configur e the fifo. the number of message bu ffers assigned to the receive fifo, starting from message buffer 0, can be selected. writ ing the fsizr register is possible only during the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved fsiz5 fsiz4 fsiz3 fsiz2 fsiz1 fsiz0 r r rw* rw* rw* rw* rw* rw* figure 3-89. fifo size register table 3-9. fifo size fsiz[5:0] fifo size 000000 no fifo is defined 000001 only message buffer 0 000010 message buffer 0?message buffer 1 000011 message buffer 0?message buffer 2 ?? 111001 message buffer 0?message buffer 56 111010 message buffer 0?message buffer 57 others message buffer 0?message buffer 58 mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 126 freescale semiconductor 3.2.3.7.2 message buffer c ontrol, configuration and st atus n register, n = [0:58] (bufcsnr) address bufcs0r=0x200, bufcs1r=0x204, ?, bufcs57r=0x2e4, bufcs58r=0x2e8. bufcsnr=0x200 + 0x4*dec2hex(n) reset iflg, iena, cfg and valid bits are reset to 0, others ? in undefined state for a description of these regist ers and the bit access scheme, see section 3.4.1, ?message buffer control, configuration and status register ?. 3.2.3.7.3 active transmit buffer frame id register (atbfrid) address 0x180 reset undefined state for a description of this register and the bit access scheme, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 valid tt ccfe bt datupd chb cha bufcmt ******** 76543210 reserved lock reserved reserved iena iflg reserved cfg r*rr**r* figure 3-90. message buffer control, conf iguration and status n register, n = [0:58] 15 14 13 12 11 10 9 8 r* pp nfi sync startup id10 id9 id8 rw rw* r r r rw* rw* rw* 76543210 id7 id6 id5 id4 id3 id2 id1 id0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-91. active transmit buffer frame id register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 127 3.2.3.7.4 active transmit buffer cycle counter and paylo ad length register (atbccplr) address 0x182 reset undefined state note the host may read the cycl_cnt[5:0] bits but, as those bits are not updated by the cc, they will be in an undefined state. for a description of this register and the bit access scheme, refer to section 3.5, ?message buffer handling and operations ?. 3.2.3.7.5 active transmit buffer header crc register (atbcrcr) address 0x184 reset undefined state for a description of this register and the bit access scheme, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 reserved reserved cycl_cnt5 cycl_cnt4 cycl_cnt3 cycl_cnt2 cycl_cnt1 cycl_cnt0 r r r* r* r* r* r* r* 76543210 reserved len6 len5 len4 len3 len2 len1 len0 r rw* rw* rw* rw* rw* rw* rw* figure 3-92. active transmit buffer cycle counter and payload length register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved hcrc10 hcrc9 hcrc8 rrrrrrw*rw*rw* 76543210 hcrc7 hcrc6 hcrc5 hcrc4 hcrc3 hcrc2 hcrc1 hcrc0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-93. active transmit buffer header crc register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 128 freescale semiconductor 3.2.3.7.6 active transmit buffer data n register, n = [0:15] (atbdatanr) address atbdata0r=0x186 ? atbdata15r=0x1a4 reset undefined state for a description of these registers, refer to section 3.5, ?message buffer handling and operations ?. 3.2.3.7.7 active transmit buff er message buffer slot status vector register (atbmbssvr) address 0x1a6 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 data(2n+1)15 data(2n+1)14 data(2n+1)13 data(2n+1)12 data(2n+1)11 data(2n+1)10 data(2n+1)9 data(2n+1)8 rw rw rw rw rw rw rw rw 76543210 data(2n)7 data(2n)6 data(2n)5 data(2n)4 data(2n)3 data(2n)2 data(2n)1 data(2n)0 rw rw rw rw rw rw rw rw figure 3-94. active transmit buffer data n register, n = [0:15] 15 14 13 12 11 10 9 8 reserved reserved reserved reserv ed reserved reserved reserved ch rrrrrrrr 76543210 vce syncf nullf supf serr cerr bviol txcon rrrrrrrrh figure 3-95. active transmit buffer message buffer slot status vector register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 129 3.2.3.7.8 active receive buffer frame id register (arbfrid) address 0x140 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 3.2.3.7.9 active receive buffer cycl e counter and payload length register (arbccplr) address 0x142 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 r* pp nfi sync startup id10 id9 id8 rh rh rh rh rh rw* rw* rw* 76543210 id7 id6 id5 id4 id3 id2 id1 id0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-96. active receive buffer frame id register 15 14 13 12 11 10 9 8 reserved reserved cycl_cnt5 cycl_cnt4 cycl_cnt3 cycl_cnt2 cycl_cnt1 cycl_cnt0 r r rh rh rh rh rh rh 76543210 reserved len6 len5 len4 len3 len2 len1 len0 r rhrhrhrhrhrhrh figure 3-97. active receive buffer cycle counter and payload length register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 130 freescale semiconductor 3.2.3.7.10 active receive buffer header crc regi ster (arbcrcr) address 0x144 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 3.2.3.7.11 active receive buffer data n register, n = [0:15] (arbdatanr) address arbdata0r=0x146 ? arbdata15r=0x164 reset undefined state for a description of these registers, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved hcrc10 hcrc9 hcrc8 rrrrrrhrhrh 76543210 hcrc7 hcrc6 hcrc5 hcrc4 hcrc3 hcrc2 hcrc1 hcrc0 rh rh rh rh rh rh rh rh figure 3-98. active receive buffer header crc register 15 14 13 12 11 10 9 8 data(2n+1)15 data(2n+1)14 data(2n+1)13 data(2n+1)12 data(2n+1)11 data(2n+1)10 data(2n+1)9 data(2n+1)8 rh rh rh rh rh rh rh rh 76543210 data(2n)7 data(2n)6 data(2n)5 data(2n)4 data(2n)3 data(2n)2 data(2n)1 data(2n)0 rh rh rh rh rh rh rh rh figure 3-99. active receive buffer data n register, n = [0:15] memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 131 3.2.3.7.12 active receive buffer message buffer slot status vector register (arbmbssvr) address 0x166 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 3.2.3.7.13 active fifo buffer frame id regist er (afbfrid) address 0x100 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 reserved reserved reserved reserv ed reserved reserved reserved ch rrrrrrrr 76543210 vce syncf nullf supf serr cerr bviol txcon rh rh rh rh rh rh rh r figure 3-100. active receive buffer message buffer slot status vector register 15 14 13 12 11 10 9 8 r* pp nfi sync startup id10 id9 id8 rh rh rh rh rh rh rh rh 76543210 id7 id6 id5 id4 id3 id2 id1 id0 rh rh rh rh rh rh rh rh figure 3-101. active fifo buffer frame id register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 132 freescale semiconductor 3.2.3.7.14 active fifo buffer cycle count er and payload length r egister (afbccplr) address 0x102 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 3.2.3.7.15 active fifo buffer header crc regist er (afbcrcr) address 0x104 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 reserved reserved cycl_cnt5 cycl_cnt4 cycl_cnt3 cycl_cnt2 cycl_cnt1 cycl_cnt0 r r rh rh rh rh rh rh 76543210 reserved len6 len5 len4 len3 len2 len1 len0 r rhrhrhrhrhrhrh figure 3-102. active fifo buffer cycle counter and payload length register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved hcrc10 hcrc9 hcrc8 rrrrrrhrhrh 76543210 hcrc7 hcrc6 hcrc5 hcrc4 hcrc3 hcrc2 hcrc1 hcrc0 rh rh rh rh rh rh rh rh figure 3-103. active fifo buffer header crc register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 133 3.2.3.7.16 active fifo buffer data n register, n = [0:15] (afbdatanr) address arfbdata0r=0x106 ? arfbdata15r=0x124 reset undefined state for a description of these registers, refer to section 3.5, ?message buffer handling and operations ?. 3.2.3.7.17 active fifo buffer message buffer slot status vector register (afbmbssvr) address 0x126 reset undefined state for a description of this register, refer to section 3.5, ?message buffer handling and operations ?. 15 14 13 12 11 10 9 8 data(2n+1)15 data(2n+1)14 data(2n+1)13 data(2n+1)12 data(2n+1)11 data(2n+1)10 data(2n+1)9 data(2n+1)8 rh rh rh rh rh rh rh rh 76543210 data(2n)7 data(2n)6 data(2n)5 data(2n)4 data(2n)3 data(2n)2 data(2n)1 data(2n)0 rh rh rh rh rh rh rh rh figure 3-104. active fifo buffer data n register, n = [0:15] 15 14 13 12 11 10 9 8 reserved reserved reserved reserv ed reserved reserved reserved ch rrrrrrrr 76543210 vce syncf nullf supf serr cerr bviol txcon rh rh rh rh rh rh rh r figure 3-105. active fifo buffer message buffer slot status vector register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 134 freescale semiconductor 3.2.3.8 filtering related registers 3.2.3.8.1 sync frame acceptance filt er value register (synfafvr) address 0xf0 reset undefined state if ensynff bit is set (see section 3.2.3.2.1, ?module configuration register 0 (mcr0) ?), every valid sync frame with the identifier id must fulfill the following condition before it s arrival time measurement values can be used for the clock synchronization. an identifier is accepted when: ( not((id xor synfafv) and synfafm) and not(id == synfrf) ) == true eqn. 3-12 this register may be written only in the configuration state. 3.2.3.8.2 sync frame acceptance fi lter mask register (synfafmr) address 0xee reset undefined state synfafm[10:0] 0 ? this bit position is ?don't care? for acceptance. 1 ? this bit of the identifier must be identical to the corresponding bit in the acceptance value, for it to be accepted by the sync frame acceptance filter. this register may be written only in the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved synfafv10 synfafv9 synfafv8 rrrrrrw*rw*rw* 76543210 synfafv7 synfafv6 synfafv5 synfafv4 synfafv3 synfafv2 synfafv1 synfafv0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-106. sync frame acceptance filter value register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved synfafm10 synfafm9 synfafm8 rrrrrrw*rw*rw* 76543210 synfafm7 synfafm6 synfafm5 synfafm4 synfafm3 synfafm2 synfafm1 synfafm0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-107. sync frame acceptance filter mask register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 135 3.2.3.8.3 sync frame rejection filter register (synfrfr) address 0xf2 reset undefined state if the ensynff bit is set (see section 3.2.3.2.1, ?module confi guration register 0 (mcr0) ?), this register is used to identify a sync frame id whose arrival time measurement values are to be rejected for clock synchronization. note that this register can be written at any time by the host, unlike synfafmr and synfafvr (see section 3.2.3.8.2, ?sync frame acceptance filter mask register (synfafmr) ? and section 3.2.3.8.1, ?sync frame acceptance f ilter value register (synfafvr) ?). note to ensure correct operation of the cc , the host should update this register only during the nit. 3.2.3.8.4 cycle counter filter n register , n = [0:58] (ccfnr) address ccf0r=0x202, ccf1r=0x206 , ?, ccf57r=0x2e6 , ccf58r=0x2ea. ccfnr=0x202 + 0x4*dec2hex(n) reset undefined state each cycle counter filter register is related to an appropriate message buffer: ccf0r to message buffer 0, ccf1r to message buffer 1, ? , ccf58r to mes sage buffer 58. (for more information, refer to section , ?receive, receive fifo, and transm it message buffers are accessible to the host mcu only through the active receive, active transmit, and active receive fifo buffers. ?). 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved synfrf10 synfrf9 synfrf8 rrrrrrwrwrw 76543210 synfrf7 synfrf6 synfrf5 synfrf4 synfrf3 synfrf2 synfrf1 synfrf0 rw rw rw rw rw rw rw rw figure 3-108. sync frame rejection filter register 15 14 13 12 11 10 9 8 reserved reserved ccm5 ccm4 ccm3 ccm2 ccm1 ccm0 r r rw* rw* rw* rw* rw* rw* 76543210 reserved reserved ccv5 ccv4 ccv3 ccv2 ccv1 ccv0 r r rw* rw* rw* rw* rw* rw* figure 3-109. cycle counter filter n register, n = [0:58] mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 136 freescale semiconductor ccv[0:5] ? cycle count value n bit[0:5] these bits determine the cycle count valu e to be used for the cycle filtering. ccm[0:5] ? cycle count mask n bit[0:5] these bits define the mask us ed in the filtering process. 0 ? this bit of the cycle counter is not used for filtering. 1 ? this bit of the cycle counter is used for filtering. for a description of the read and write character of each bit-field, refer to section 3.4.1, ?message buffer control, configuration and status register ? and section 3.4.2, ?message buffer filter registers ?. 3.2.3.8.5 fifo acceptance filter message id value register (fafmidvr) address 0x1c reset 0x0 fmdafv[0:15] these bit-fields define the fifo m essage id filter value, for compa rison with the message id field of received frames. it defines the accep table pattern value of the message id to be received. these bits may be written only in the configuration state. 3.2.3.8.6 fifo acceptance filter message id mask register (fafmidmr) address 0x1e reset 0x0 15 14 13 12 11 10 9 8 fmdafv15 fmdafv14 fmdafv13 fmdafv12 fmdafv11 fmdafv10 fmdafv9 fmdafv8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 fmdafv7 fmdafv6 fmdafv5 fmdafv4 fmdafv3 fmdafv2 fmdafv1 fmdafv0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-110. fifo acceptance filter message id value register 15 14 13 12 11 10 9 8 fmdafm15 fmdafm14 fmdafm13 fmdafm12 fmdafm11 fmdafm10 fmdafm9 fmdafm8 rw* rw* rw* rw* rw* rw* rw* rw* 76543210 fmdafm7 fmdafm6 fmdafm5 fmdafm4 fmdafm3 fmdafm2 fmdafm1 fmdafm0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-111. fifo acceptance filter message id mask register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 137 fmdafm[0:15] these bit-fields define the mask for the fifo message id filter. 0 ? this bit in the message id field of a received frame is not cons idered for acceptance filtering. 1 ? this bit in the message id field of a receiv ed frame is used for the acceptance filtering. these bits may be written onl y in the configuration state. 3.2.3.8.7 fifo acceptance/rejection fi lter channel register (fafchr) address 0x1a reset 0x0 fchaafv, fchbafv these are fifo channel filtering value bits. they de fine the channel from which the received frame will be accepted or rejected. thes e bits may be written only in the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved rrrrrrrr 76543210 reserved reserved reserved reserved reserved reserved fchbafv fchaafv rrrrrrrw*rw* figure 3-112. fifo acceptance/rejection filter channel register table 3-10. fifo channel filtering configuration fchaafv fchbafv receive message buffer store valid rx frame 1 1 frame received on both channels are accepted or rejected 1 0 frame received on channel a is accepted or rejected 0 1 frame received on channel b is accepted or rejected 0 0 ignore frame mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 138 freescale semiconductor 3.2.3.8.8 fifo rejection filter fr ame id value register (frffidvr) address 0x20 reset 0x0 ffidrfv[0:10] this field contains the fifo frame id rejection filt er value, for comparison with frame id fields of received frames. it defines the acceptable pattern value of the frame id to be re jected. these bits may be written only in the configuration state. 3.2.3.8.9 fifo rejection filter fr ame id mask register (frffidmr) address 0x22 reset 0x0 ffidrfm[0:10] these bit-fields indicate the mask fo r the fifo rejection frame id filter. 0 ? this bit of the internal slot id (when a frame was r eceived) is not considered for the rejection filtering. 1 ? this bit of the internal slot id (when a frame was received) is used for the rejection filtering. these bits may be written onl y in the configuration state. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved ffidrfv10 ffidrfv9 ffidrfv8 rrrrrrw*rw*rw* 76543210 ffidrfv7 ffidrfv6 ffidrfv5 ffidrfv4 ff idrfv3 ffidrfv2 ff idrfv1 ffidrfv0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-113. fifo rejection f ilter frame id value register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved ffidrfm10 ffidrfm9 ffidrfm8 rrrrrrw*rw*rw* 76543210 ffidrfm7 ffidrfm6 ffidrf m5 ffidrfm4 ffidrfm3 ff idrfm2 ffidrfm1 ffidrfm0 rw* rw* rw* rw* rw* rw* rw* rw* figure 3-114. fifo rejection filter frame id mask register memory map and registers mfr4200 data sheet, rev. 0 freescale semiconductor 139 3.2.3.9 timer related registers the cc provides two timers with time r interrupt configurati on registers for setting interrupts for specific points of global time. each ti mer contains two parameters: 1. cycle set: a 9-bit register is used to specify in which set of co mmunication cycles the interrupt will occur. it consists of two fields, the base cycl e [b] and the cycle repetiti on [c]. the set of cycle numbers where the interrupt is to generated is determined from these two fields using the formula: b + n*2^c (n = 0, 1, 2, ?) eqn. 3-13 where: ? b is a 6-bit cycle number used to identify the initial value for generating the cycle set. ? c is a 3-bit value used to determine a constant repetition factor to be added to the base cycle (c=0?6) ? b must be smaller than 2^c: b<2^c. eqn. 3-14 2. macrotick offset: this 16-bit value is the macrotick offs et from the beginning of the cycle in which the interrupt is to occur. the interrupt occurs at this offset for each cycle in the interrupt cycle set. 3.2.3.9.1 timer interrupt configuration register 0 cycle set (ticr0cs) address 0x30 reset 0x0 this register holds base cycle and cycle repetition values for timer 0. a hard reset clears the register. bct[0:5] base cycle value for timer 0. cr[0:2] cycle repetition value for timer 0. 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved cr2 cr1 cr0 rrrrrrwrwrw 76543210 reserved reserved bct5 bct4 bct3 bct2 bct1 bct0 r r rw rw rw rw rw rw figure 3-115. timer interrupt configuration register 0 cycle set mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 140 freescale semiconductor 3.2.3.9.2 timer interrupt c onfiguration register 0 m acrotick offset (ticr0mo) address 0x32 reset 0x0 this register holds the macrotic k offset value for timer 0. a hard reset clears the register. 3.2.3.9.3 timer interrupt configuration register 1 cycle set (ticr1cs) address 0x34 reset 0x0 this register holds base cycle and cycle repetition values for timer 1. a hard reset clears the register. bct[0:5] base cycle value for timer 1. cr[0:2] cycle repetition value for timer 1. 15 14 13 12 11 10 9 8 mo15 mo14 mo13 mo12 mo11 mo10 mo9 mo8 rw rw rw rw rw rw rw rw 76543210 mo7 mo6 mo5 mo4 mo3 mo2 mo1 mo0 rw rw rw rw rw rw rw rw figure 3-116. timer interrupt configuration register 0 macrotick offset 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved cr2 cr1 cr0 rrrrrrwrwrw 76543210 reserved reserved bct5 bct4 bct3 bct2 bct1 bct0 r r rw rw rw rw rw rw figure 3-117. timer interrupt configuration register 1 cycle set message buffer mfr4200 data sheet, rev. 0 freescale semiconductor 141 3.2.3.9.4 timer interrupt c onfiguration register 1 m acrotick offset (ticr1mo) address 0x36 reset 0x0 the timer interrupt configuration regi ster 1 macrotick offset holds the macrotick offset value for timer 1. a hard reset clears the register. 3.3 message buffer receive, receive fifo, and trans mit message buffers ar e accessible to the host mcu only through the active receive, active transmit, and active receive fifo buffers. 3.3.1 message buffer layout the layout shown in below, apply to tran smit, receive buffer, and fifo buffers. 15 14 13 12 11 10 9 8 mo15 mo14 mo13 mo12 mo11 mo10 mo9 mo8 rw rw rw rw rw rw rw rw 76543210 mo7 mo6 mo5 mo4 mo3 mo2 mo1 mo0 rw rw rw rw rw rw rw rw figure 3-118. timer interrupt co nfiguration register 1 high table 3-11. receive message buffer layout 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r* ro pp ro nfi ro sync ro start up ro frame id (11 bits) ro_no/wr_cs 1 r nu cycle count (6 bits) ro r nu payloadlength (7 bits) ro 2 r nu header crc (11 bits) ro 3 message id1/data1/nmvector1 ro message id0/data0/nmvector0 ro 4 data3/nmvector3 ro data2/nmvector2 ro 5 data5/nmvector5 ro data4/nmvector4 ro 6 data7/nmvector7 ro data6/nmvector6 ro 7 data9/nmvector9 ro data8/nmvector8 ro 8 data11/nmvector11 ro data10/nmvector10 ro 9 data13 ro data12 ro ? ? ro ? ro 18 data31 ro data30 ro 19 message buffer slot status vector ro mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 142 freescale semiconductor note the host cannot access the cc part of a double transmit message buffer. cc raises a locking error if the host tries to lock the cc part of a double transmit message buffer. table 3-12. receive fifo message buffer layout 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r* ro pp ro nfi ro sync ro start up ro frame id (11 bits) ro 1 r nu cycle count (6 bits) ro r nu payloadlength (7 bits) ro 2 r nu header crc (11 bits) ro 3 message id1/data1/nmvector1 ro message id0/data0/nmvector0 ro 4 data3/nmvector3 ro data2/nmvector2 ro 5 data5/nmvector5 ro data4/nmvector4 ro 6 data7/nmvector7 ro data6/nmvector6 ro 7 data9/nmvector9 ro data8/nmvector8 ro 8 data11/nmvector11 ro data10/nmvector10 ro 9 data13 ro data12 ro ? ? ro ? ro 18 data31 ro data30 ro 19 message buffer slot status vector ro table 3-13. transmit message buffer layout 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r* wr pp tx_cs_no nfi nu sync nu start up nu frame id (11 bits) tx_cs_no 1 r nu cycle count (6 bits) nu r nu payloadlength (7 bits) tx_cs_no 2 r nu header crc (11 bits) tx_cs_no 3 message id1/data1/nmvector1 wr message id0/data0/nmvector0 wr 4 data3/nmvector3 wr data2/nmvector2 wr 5 data5/nmvector5 wr data4/nmvector4 6 data7/nmvector7 wr data6/nmvector6 wr 7 data9/nmvector9 wr data8/nmvector8 wr 8 data11/nmvector11 wr data10/nmvector10 wr 9 data13 wr data12 wr ? ? wr ? wr 18 data31 wr data30 wr 19 message buffer slot status vector ro message buffer mfr4200 data sheet, rev. 0 freescale semiconductor 143 where: the size of the data field in the mfr4200 is limited to 32 bytes. 3.3.2 message buffer field descriptions 3.3.2.1 id[10:0] ? frame id field each transmit and receive message bu ffer and the fifo buffer contains a frame id field. this field is interpreted differently for receiv e message buffers, transmit messag e buffers, and the receive fifo. ro_no/wr_cs host read access; host write a ccess during the configuration state only tx_cs_no host read access; host write access: ? during the configuration state for all transmit message buffers ? during normal mode of operation for buffer s configured for the dynamic segment of the communication cycle (read-only access for static segment buffers) ro host read-only access wr host read/write access nu reserved or read-only bits not used by the cc during operation table 3-14. mapping between buffer layout and active receive/transmit/fifo message buffers message buffer layout active fifo/receive/transmit message buffers register r * p p n fi syn c star t up frame id (11 bits) active fifo/receive/transmit buffer frame id register r cycle count (6 bits) r payloadlength (7 bits) active fifo/receive/transmit buffer cycle counter and payload length register r header crc (11 bits) active fifo/receive/transmit buffer header crc register message id1/data1/nmvector1 message id0/data0/nmvector0 active fifo/receive/transmi t buffer data 0 register data3/nmvector3 data2/nmvector2 active fifo/r eceive/transmit buffer data 1 register data5/nmvector5 data4/nmvector4 active fifo/r eceive/transmit buffer data 2 register data7/nmvector7 data6/nmvector6 active fifo/r eceive/transmit buffer data 3 register data9/nmvector9 data8/nmvector8 active fifo/r eceive/transmit buffer data 4 register data11/nmvector11 data10/nmvector10 active fifo/receive/transmit buffer data 5 register data13 data12 active fifo/receive/t ransmit buffer data 6 register ?? ? data31 data30 active fifo/receive/t ransmit buffer data 15 register message buffer slot status vector active fifo/rec eive/transmit buffer message buffer slot status vector register mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 144 freescale semiconductor receive message buffers: the frame id field contains a frame id filtering valu e. a received frame is stored in the first receive message buffer with a filter matching the received frame id. the channel and cycle counter receive filtering criteria must also be met. transmit message buffers: the frame id field in the message buffer is used to determine the appropriate slot for frame transmission. the frame is transmitted in the time slot correspondi ng to the frame id, provided the channel and cycle counter criteria are also met. receive fifo message buffer: the frame id field in each el ement of the receive fifo buffer stores a received frame id value, if the frame is accepted by the fifo acceptance fi lter and not rejected by the fifo re jection filter and if there is no matching dedicated receive message buffer. for more inform ation on fifo filters, refer to section 3.2.3.8, ?filtering related registers ?) 3.3.2.2 r* ? reserved bit the reserved bit r* corresponds to th e reserved bit in the header of the flexray frame. the controller transmits that bit within the frame header. this bit must be cleared by the host for ps v1.9/v2.0 compliant operation. 3.3.2.3 r ? reserved bits these bits are reserved for future use and have no correlation with the r* bit. 3.3.2.4 pp ? payload preamble bit the payload preamble bit indicates that a static frame?s payload data hold a network management vector, and that a dynamic frame?s payload da ta hold a message id, respectively. 3.3.2.5 nfi ? null frame indication bit the null frame indication bit shows the value of the nul l frame indication flag fo r received frames stored in message receive/fifo buffers. this bit has no function for transmi t message buffers. the nullf bit, described in section 3.3.3, ?message buffer slot status vector ?, indicates the reception of a null frame on the physical layer. note during the transition from the hard rese t to the configurat ion state, the cc initializes the nfi bits of all buffers to ?0?. in the normal passive and active states, the cc receives but does not st ore null frames. therefore, after the first reception and storage of a valid r eceive frame?s header and payload data to a receive message/fifo buffer, the cc sets the nfi bit of that buffer. from that moment on, this bit remains set. message buffer mfr4200 data sheet, rev. 0 freescale semiconductor 145 3.3.2.6 cyclcnt[5:0] ? cycle counter the cycle counter field holds the cc cy cle counter value at fram e reception time. this field is not used in message buffers configured for transmission. 3.3.2.7 len[6: 0] ? payload length the payload length field holds the num ber of words (1 word = 2 bytes) contained in the payload segment of the frame. receive message buffers and receive fifo: the payload field indicates the value of the payload length field in the received frame (see section 3.3.3, ?message buffer slot status vector ). transmit message buffers: the payload field indicates the num ber of words to be transmitted. if the host writes a payload length not equal to splr in to a static frame, the cc generates the chi error interrupt splme (see section 3.2.3.6.3, ?chi error register (chier) ?). if the host writes a payload lengt h greater than mpldr into a dynami c frame, the cc generates the chi error interrupt mdple (see section 3.2.3.6.3, ?chi error register (chier) ?). note that the size of the data field in the mfr4200 is limited to 32 bytes (see section 3.1.1, ?mfr4200 features ?). 3.3.2.8 hcrc[10:0] ? header crc the header crc field contains a cy clic redundancy check code (crc) computed over the sync bit, startup bit, the frame id, and the payload length fields of the frame. receive message buffers and receive fifo: the header crc field contains the header crc of the semantically vali d and syntactically correct received frame. transmit message buffers: the header crc field contains the header crc value calculated and prov ided by the host. note that the controller does not check if the header crc provided by the host is correct. 3.3.2.9 sync ? sync bit the sync bit determines whether the frame is to be used for clock synchronization. receive message buffers and receive fifo: the bit contains the sync bi t of the stored frame. this bit is updated only when a new semantically valid frame matching the buffer filters has been stored in the message buffer. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 146 freescale semiconductor transmit message buffers: this bit is not used. note the host sets up the slot id determ ining the slot during which the cc transmits a sync frame via the s ync frame register syncfr (see section 3.2.3.3.29, ?sync frame register (syncfr) ?). 3.3.2.10 startup ? startup bit the startup bit determines whether the frame is to be used for clock sync hronization during startup. receive message buffers and receive fifo the bit contains the startup bit of the stored frame. this bit is updated only when a new semantically valid frame matching the buffer filters ha s been stored in the message buffer. transmit message buffers this bit is not used. note the host sets up the startup bit for tr ansmit frames via the startup bit sup in register syncfr (see section 3.2.3.3.29, ?sync frame register (syncfr) ?). 3.3.3 message buffer slot status vector all message buffers, including transmit buffers, comp rise a message buffer slot status vector holding a 9-bit wide slot stat us information field. 15 14 13 12 11 10 9 8 reserved reserved reserved reserv ed reserved reserved reserved ch rrrrrrrr 76543210 vce syncf nullf supf serr cerr bviol txcon rrrrrrrrh* figure 3-119. transmit message buffer slot status vector message buffer mfr4200 data sheet, rev. 0 freescale semiconductor 147 note the cc indicates status informati on for transmit message buffers only, in the txcon bit; the remaining bits are used to indicat ed receive status information. therefore, if a message buffer is configured as a receive or receive fifo message buffer, its txc on bit is not used by the cc. if a message buffer is configured as a transmit message buffer, only its txcon bit is updated by the cc, whil e the remaining bits are not used by the controller. refer to table 3-4 for slot status monitoring availability in different protocol states. after reception of a null frame or an invalid frame, the controller updates only the slot status vector of a sele cted receive message buffer or fifo buffer. other fields (see table 3-11 and table 3-12 ) of those buffers stay unaltered. after reception of a va lid frame, the co ntroller updates the slot status vector and the remainder of the rece ive message buffer or fifo buffer. after transmission of a frame, the controller updates the slot status vector in the current transmit message buffer. the controller updates a message buffer assigned to slot n within the first macrotick of the slot n+1. empty static slots exhibit sl ot status 0x0000 on channel a and 0x0100 on channel b. 3.3.3.1 txcon ? tx conflict this flag indicates transmissi on conflicts, i.e. indicates that a recept ion is in progress when the controller starts transmission. this bit indicates conflicts during transmissi on in static and dynamic segments. 0 ? no transmission conflict detected. 1 ? transmission conflict detected. 15 14 13 12 11 10 9 8 reserved reserved reserved reserv ed reserved reserved reserved ch rrrrrrrrh* 76543210 vce syncf nullf supf serr cerr bviol txcon rh* rh* rh* rh* rh* rh* rh* r figure 3-120. receive and receive fifo message buffer slot status vector mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 148 freescale semiconductor 3.3.3.2 bviol ? boundary violation this flag provides information about media activity at slot boundaries (eit her the end or the beginning of the current slot). note that this is not necessarily an error condition, as a seman tically valid frame can be received between the slot boundaries, provided that th e idle conditions before and after the frame are fulfilled. 0 ? no media activity detected at slot boundaries. 1 ? media activity detected at slot boundaries. 3.3.3.3 cerr ? content error this flag indicates the reception of a semantically incorrect frame. 0 ? no content error occurred in current slot. 1 ? content error occu rred in current slot. 3.3.3.4 serr ? syntax error this flag indicates the reception of a syntactically incorrect frame. 0 ? no syntax error occurred in current slot. 1 ? syntax error occurred in current slot. 3.3.3.5 supf ? startup frame indication this flag indicates the reception of a fr ame header having its startup bit set. 0 ? no syntactically correct start up frame received in current slot. 1 ? syntactically correct startup frame received in current slot. 3.3.3.6 nullf ? null frame indication this flag indicates the reception of a frame he ader having its null frame indication bit set. 0 ? no syntactically correct null frame received in current slot. 1 ? syntactically correct null fra me received in current slot. 3.3.3.7 syncf ? sync frame indication this flag indicates the reception of a frame header having its sync frame indication set. 0 ? no syntactically correct sync frame received in current slot. 1 ? syntactically corr ect sync frame received in current slot. message buffer mfr4200 data sheet, rev. 0 freescale semiconductor 149 3.3.3.8 vce ? valid communication element this flag indicates the reception of a valid communi cation element. a valid communication element is either a syntactically and seman tically correct frame or symbol. 0 ? no valid communication elemen t received in current slot. 1 ? valid frame received in current slot. 3.3.3.9 ch ? channel this flag indicates the channel the slot status refers to. 0 ? slot status of channel a. 1 ? slot status of channel b. 3.3.4 message id if the payload preamble bit pp is set, the message id field holds the message id of a dynamic frame located in the message buffer. the fifo filter may use th e received message id fo r message id filtering. 3.3.5 nmvector fields if the payload preamble bit pp is set, the network management vect or fields hold the network management vector of a static frame lo cated in the message buffer. 3.3.6 data[0:31] ? data fields receive message buffers: the data fields store received frame payload data , if all the receive filt ering criteria are met. transmit message buffers: the host writes these data fields wi th payload data to be transmitted. receive fifo: the data fields in the fifo buffer stores a received frame? s payload data values if the channel, message id, and cycle counter are accepted by the configured receive fifo accep tance filter value and mask, and not rejected by the configured recei ve fifo rejection filter value a nd mask, and if th ere is no matching dedicated receive message buffer in the mailbox. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 150 freescale semiconductor 3.4 message buffer control, config uration, status and filtering register set 3.4.1 message buffer control, co nfiguration and status register message buffer control, configurati on and status register (bufcsnr[0 :58]). the bufcs[0:58] layout is the same for receive message buffer s, transmit message buffers and fi fo. however, the access rules for register bits depend on various modes of operation and on the buffer configuration. bit 15 14 13 12 11 10 9 8 name valid ro_no/wr_cs tt nu ccfe ro_no/wr_cs bt nu datupd ro_no/wr_cs chb ro_no/wr_cs cha ro_no/wr_cs bufcmt nu hard reset 0 access rwh* r rw* r rwh* rw* rw* r bit 7 6 5 4 3 2 1 0 name reserved nu lock wr reserved nu reserved nu iena wr iflg ro reserved nu cfg ro_no/wr_cs hard reset 0 0 0 access r rw r r rw rh r rw* figure 3-121. bufcsnr of a receive message buffer bit 151413 121110 9 8 name valid ro tt wr ccfe ro_no/wr_cs bt ro_no/wr_cs datupd nu chb ro_no/wr_cs cha ro_no/wr_cs bufcmt wr hard reset 0 access rh rw rw* rw* r rw* rw* rw bit 7 6 5 4 3 2 1 0 name reserved nu lock wr reserved nu reserved nu iena wr iflg ro reserved nu cfg ro_no/wr_cs hard reset 0 0 0 access r rw r r rw rh r rw* figure 3-122. bufcsnr of a transmit message single buffer for the dynamic segment message buffer control, configuration, status and filtering register set mfr4200 data sheet, rev. 0 freescale semiconductor 151 bit151413121110 9 8 name valid ro tt ro_no/wr_cs ccfe ro_no/wr_cs bt ro_no/wr_cs datupd nu chb ro_no/wr_cs cha ro_no/wr_cs bufcmt wr hard reset 0 access rh rw* rw* rw* r rw* rw* rw bit7 6 5 432 1 0 name reserved nu lock wr reserved nu reserved nu iena wr iflg ro reserved nu cfg ro_no/wr_cs hard reset 0 0 0 access r rw r r rw rh r rw* figure 3-123. bufcsnr of a host part transmit message buffer of a double tx buffer for the dynamic segment bit1514 13 121110 9 8 name valid ro tt ro_no/wr_cs ccfe ro_no/wr_cs bt ro_no/wr_cs datupd nu chb ro_no/wr_cs cha ro_no/wr_cs bufcmt wr hard reset 0 access rh rw* rw* rw* r rw* rw* rw bit76543210 name reserved nu lock wr reserved nu reserved nu iena wr iflg ro reserved nu cfg ro_no/wr_cs hard reset 0 0 0 access r rw r r rw rh r rw* figure 3-124. bufcsnr of a host part transmit message buffer of a double tx buffer for the static segment bit15 14 13 121110 9 8 name valid ro tt ro_no/wr_cs ccfe ro_no/wr_cs bt ro_no/wr_cs datupd nu chb ro_no/wr_cs cha ro_no/wr_cs bufcmt wr hard reset 0 access rh rw* rw* rw* r rw* rw* rw bit 7 6 5 4 3 2 1 0 name reserved nu lock wr reserved nu reserved nu iena wr iflg ro reserved nu cfg ro_no/wr_cs hard reset 0 0 0 access r rw r r rw rh r rw* figure 3-125. bufcsnr of a single transmit message buffer for the static segment mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 152 freescale semiconductor where: 3.4.1.1 cfg ? message buffer configuration bit this bit is used to configure the corresponding buffer as a transmit or receive message buffer. cfg bit is cleared by a hard reset. the access to this bit is defined in table 3-16 . 1 ? the corresponding buffer is configur ed as a transmit message buffer. 0 ? the corresponding buffer is configur ed as a receive message buffer. bit 15 14 13 12 11 10 9 8 name valid ro tt ro ccfe ro bt ro datupd nu chb ro cha ro bufcmt ro hard reset 0 access rh r r r r r r r bit7654 3 210 name reserved nu lock nu reserved nu reserved nu iena ro iflg ro reserved nu cfg ro hard reset 0 0 0 access r r r r r rh r r figure 3-126. bufcsnr of a cc part transmit message buffer of a double tx buffer for dynamic and static segment bit 15 14 13 12 11 10 9 8 name valid nu tt nu ccfe nu bt nu datupd nu chb nu cha nu bufcmt nu hard reset 0 access r r r r r r r r bit7654 3 210 name reserved nu lock wr reserved nu reserved nu iena nu iflg nu reserved nu cfg nu hard reset 0 0 0 access r rwh r r r r r r figure 3-127. bufcsnr of fifo buffer ro_no/wr_cs host read/write access during the configur ation state, in other states ? host read access; ro host read-only access wr host read/write access nu reserved or not used message buffer control, configuration, status and filtering register set mfr4200 data sheet, rev. 0 freescale semiconductor 153 3.4.1.2 iflg ? interrupt status flag the iflg flag is provided by the cc. it performs di fferent functions depending on the configuration of the corresponding message buffer. receive message buffer: the flag indicates that the contro ller has updated the receiv e message buffer due to frame reception (update of data fields and the slot status v ector after reception of a valid frame, or update of the sl ot status vector after reception of an invalid fr ame). the host can clear the flag by a buffer lock operation. 1 ? the controller sets the flag wh en the receive message buffer wa s updated after a frame reception. the host must process received da ta and clear the iflg bit. 0 ? the message buffer is not updated, or the host h as cleared the iflg bit im plicitly by locking the message buffer. transmit message buffer: the flag indicates that the message bu ffer is empty, or that the controll er has transmitted a frame from that message buffer. the host can clear th e flag by a buffer lock operation. 1 ? the flag is set by the controlle r when the transmit message buffer is empty/not updated (i.e. has been transmitted). the host may write new data to the buffer. 0 ? the flag is cleared implicitly by the host when the transmit message buffer is updated (i.e. locked). receive fifo buffer: the flag has no meaning; it will never be set. note 1. the iflg bit is set to the valu e of the cfg bit with each write to a bufcsn r register, during the configuration state. during nor mal operation, the controller upda tes the iflg bit after frame transmission (transmit message buffer) and after frame re ception (receive message buffer). ? if cfg is clear (receive message buffer) the cc clears the iflg bit, also, indicating that the receive message buffer does not hold new receive data. ? if cfg is set (transmit message buffer) the cc sets the iflg bit, also, indicating that the transmit message buffer is empty and wi ll be filled by the host application. 2. if the host does not write to a bufcsnr register during the configuration state, the iflg holds the value it had before it en tered the configuration state. 3.4.1.3 iena ? iflg interrupt enable this bit enables the corresponding message buffer as an iflg bit interrupt source. if the message buffer is configured as a receive message buffer, the generate d by the cc interrupt is a read interrupt. if the message buffer is configured as a transmit message buffer, the interrupt generated by the cc is a write interrupt. 1 ? the corresponding message buffer interrupt is enabled. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 154 freescale semiconductor 0 ? the corresponding message buff er interrupt is disabled. this bit is not used for the fifo. 3.4.1.4 lock ? message buffer lock request the bit has various functions depending on the conf iguration of the corresponding message buffer. the host can implicitly lock/unlock th e buffer by writing ?1? to the lo ck bit. writing a ?1? to the lock bit toggles the value of the lock bit: a buffer is locked when the lock bit read operation returns ?1?. a buffer is unlocked when the lock bit read operation returns ?0?. receive fifo: the host must lock a fifo buffer to make it accessibl e in the active receive fi fo buffer window. the host can request a fifo buffer lock by writing a ?1? to the lock bit of buffer 0, provided the fifo is configured. writing a ?0? to the lock bit has no effect on the bit. an attempt to lock the fifo through, not buffer 0, but another fifo buffer?s lock bit, causes a fifo bu ffer lock error (see section 3.2.3.6.3, ?chi error register (chier) ?). receive message buffer: the host must lock a receive messag e buffer in order to make it ac cessible in the active receive message buffer window. the host can request a message buffer lock by writing a? 1? to the lock bit. writing a ?0? to the lock bit has no effect on the bit. when the bu ffer is locked, the lock bit read operation returns ?1?. transmit message buffer: the host must lock the buffer in order to make it accessible through the active transmit message buffer window. the host can request a buffer lock by writi ng a ?1? to the lock bit. writing a ?0? to the lock bit has no effect on this bit. when the buffer is lock ed, the lock bit read operation returns ?1?. a buffer committed for transmis sion (appropriate bufcmt bit is ?1?) cannot be locked. if the host sends a lock request for the committed transmit message buffer, a lock error will be raised (see section 3.2.3.6.3, ?chi error register (chier) ?). note for more information about the locking/unlocking procedure, see section 3.5.3.4, ?active buffers locking/unlocking and locking timing ?. writing to the lock bit causes all othe r bits of a message buffer control and status register to be ignored for this write access to the buffer control register, i.e. it is not possible to upda te the buffer control register with the same write operation as toggles th e locked/unlocked status of the buffer. the lock/unlock request is not stored ? there is no pending lock request. message buffer control, configuration, status and filtering register set mfr4200 data sheet, rev. 0 freescale semiconductor 155 unlocking the buffer in the fifo m oves the fifo buffer access pointer to the next buffer in the fifo (see section 3.6, ?receive fifo function ?). so, the fifo does not support multiple consecutive locking/unlocking of the same fifo entry. the host locks the fifo buffers by setting the lock bit in fifo buffer number 0. 3.4.1.5 bufcmt ? message buffer commit flag the host commits a transmit message buffer for tr ansmission by setting the bufcmt flag of the corresponding buffer to ?1?. the cc checks the bufcmt bit of all transmit message buffers when it schedules a transmission. the cc can transmit, or put a frame from a transmit message buffer into a transmission schedule, only when the buffer is committed for transmission (b ufcmt = 1), unlocked (lock = 0), and all internal procedures on that transmit message buffer are finish ed (copying process, unlock process, a transmission). at the end of buffer transmission, the cc clears the bufcmt bits of single tr ansmit message buffers and cc part buffers of double transmit messag e buffers committed for transmission. the cc clears the bufcmt bit of a double buffer?s host part at the end of the buffer copy process. during the buffer copy process, the cc copies buffer data fr om the buffer?s cc part to the buffer?s host part. the host may set the bufcmt bit only for a locked transmit message buffer. to complete the commit operation, the host must unlock the bu ffer. thereafter, the cc indicates a successful commitment with the bufcmt set. the read operati on of a bufcmt bit always returns a ?0? for a locked buffer. 1 ? the transmit message buffer is committed for transmission. 0 ? the transmit message buffer is not committed for transmission. note this flag is related only to transmit message buffer s. reading or writing to bufcmt bit in a receive m essage buffer has no meani ng (i.e., this bit is not used). when the host writes ?1? to the bufcmt bit, that value will be stored until the cc clears it; so, only one writ e is necessary. writing a ?0? to the bufcmt location does not change its state. 3.4.1.6 cha, chb ? channel a and channel b flags cha and chb are channel filtering bits associated with each buffer. they serve as a filter for a receive message buffer, and as a control fi eld for a transmit message buffer. receive message buffer: received frames are stored if they are received on all the specified cha nnels in the channel filtering field. other filtering criteria must also be met. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 156 freescale semiconductor transmit message buffer: the content of the buffer is transmi tted only on the channels specified in the channel filtering field when the cycle counter filtering and frame id filtering criter ia are also met. receive fifo: those bits have no meaning fo r the receive fifo (refer to section 3.6, ?receive fifo function ? for more information about fifo filters) 3.4.1.7 ccfe ? cycle counter filtering enable bit the host controls the cycle counter filtering (refer to section 3.2.3.8.4, ?cycle counter filter n register, n = [0:58] (ccfnr) ?) of a buffer by the cycle counter filtering enable bit. 1 ? cycle counter filtering is enabled. 0 ? cycle counter filte ring is not performed. 3.4.1.8 datupd ? data updated datupd indicates if the frame data was or was not updated during the last ma tching slot/cycle/channel triple in the static segment according to the filter. the cc updates the datupd bi t after every static slot assigned to this buffer. the host may reset this bit during the configuration state by wr iting a ?0? to the bit. note that datupd is not reset by empty minislots in the dynamic segment. it is set, however, when a semantically valid fr ame is received in the dynamic segment. 1 ? a semantically valid (non null) frame was received during the last slot with a matching slot/cycle/channel triple. 0 ? either a frame that was not seman tically valid or a null frame was rece ived during the l ast slot with a matching slot/cycle/channel triple. 3.4.1.9 bt ? buffer type the host can configure every buffer of the cc as a single transmit message buffer or as a double message buffer. the handling and the operations for buff ers with different types are specified in section 3.5, ?message buffer handling and operations ?. 0 ? single transmit message buffer. table 3-15. channel filtering configuration cha chb transmit message buffer transmit frame receive message buffer store semantically valid received frame 1 1 on both channels ignore frame 1 0 on channel a received on channel a 0 1 on channel b received on channel b 0 0 no transmission ignore frame message buffer control, configuration, status and filtering register set mfr4200 data sheet, rev. 0 freescale semiconductor 157 1 ? double transmit message buffer. 3.4.1.10 tt ? type of transmission the host can configure the t ype of transmission used for a buffer. th erefore, the cc ca n combine two types of systems ? event and state driven systems. 0 ? event type of transmission 1 ? state type of transmission note the tt bit controls how the cc operates with the valid bit. 3.4.1.11 valid ? message buffer valid flag the semantic of this status bit depends on the configuration of the message buffer. transmit message buffer: the valid bit indicates whether a transmit buff er holds valid for transmission data or not. the cc clears the valid bit of a transmit message buffer when the host locks it. when the host has committed the buffer for tran smission (see the bufcmt bit description in section 3.4.1, ?message buffer control, configuration and status register ?) and unlocked it, the controller performs the following operations: sets the appropriate valid bit ? valid data frame. clears the valid bit when the frame has been tran smitted, if the appropriate tt bit of the buffer is clear (event type of transmission). does not change the valid bit when the frame ha s been transmitted, if the appropriate tt bit of the buffer is set (state type of transmission). 1 ? the corresponding buffer contains a seman tically valid frame to be transmitted. 0 ? the corresponding buffer does not contain a semantically valid frame to be transmitted. receive message buffer the valid bit indicates whether a r eceive message buffer holds semantically valid frame data or not. it is up to the host to reset this bit during the configur ation state. it changes to ?1? when the first valid non null frame is received. 1 ? the corresponding buffer contains semantically valid frame data. 0 ? the corresponding buffer does not cont ain semantically valid frame data. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 158 freescale semiconductor note the host can write the valid bit only during the configuration state, for receive message buffers. during all other modes of the cc this bit is read-only. 3.4.1.12 reserved ? reserved those bits are reserved for future use. reserved bit are accessible by hos t read operations only. they have an undefined state. 3.4.2 message buffer filter registers the cycle counter filter register ccfnr[ 0:58] is shown in the following figures. where: message buffer filter regist ers sets are used only for transmit and r eceive message buffers, not for the fifo. the fifo has its own filter register set (see section 3.2.3.8, ?filtering related registers ?). 3.4.2.1 cycle counter filter register (ccfnr) the operation of the filtering mechanism depe nds on the configuration of the buffer. receive message buffer: the received frame is stored only if all the following conditions are met. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved nu cycle count mask ro_no/wr_cs reserved nu cycle count value ro_no/wr_cs figure 3-128. ccfnr, transmit and receive message buffer filter registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved nu cycle count mask ro reserved nu cycle count value ro figure 3-129. ccfnr, cc part buffer of a double transmit message buffer filter registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved nu cycle count mask nu reserved nu cycle count value nu figure 3-130. ccfnr, fifo buffer filter registers ro_no/wr_cs field with host read-only access during normal o peration (host write access in configuration state only) ro field with host read-only access nu reserved or not used message buffer control, configuration, status and filtering register set mfr4200 data sheet, rev. 0 freescale semiconductor 159 the received cycle counter matches an element of the buffer?s cycle f ilter register, if cycle filtering is enabled; channel and frame id criteria are met; the received message has passe d all error checks (see the pwd: message error check chapter) transmit message buffer: the content of the buffer is transmitted, when an elem ent of the cycle filter register matches the current cycle counter, and the frame id matches the slot counter value. for a detailed description of the ccfr registers, see section 3.2.3.8.4, ?cycle counter filter n register, n = [0:58] (ccfnr) ?. 3.4.3 receive fifo filters there are two filter sets av ailable for fifo filtering: one fifo acceptance filter set, comprising the following registers: ? fifo acceptance filter message id value register (see section 3.2.3.8.5, ?fifo acceptance filter message id value register (fafmidvr) ?) ? fifo acceptance filter message id mask register (see section 3.2.3.8.6, ?fifo acceptance filter message id mask register (fafmidmr) ?) one fifo rejection filter set, comprising the following registers: ? fifo rejection filter frame id value register (see section 3.2.3.8.8, ?fifo rejection filter fr ame id value register (frffidvr) ?) ? fifo rejection filter frame id mask register (see section 3.2.3.8.9, ?fifo rejection filter fr ame id mask register (frffidmr) ?) the channels, from which the received frame will be accepted or rejected by the fi fo acceptance/rejection filters, are specified by the fafchr register (see section 3.2.3.8.7, ?fifo acceptance/rejection filter channel register (fafchr) ?). note the information from a received frame wi ll be stored in the fifo provided the following conditions are met: the receive message bu ffer filtering did not succeed, i.e. none of the configured receive message buffers has a matching filter. the message id is accepted by th e configured acceptance filter set. the frame id is not rejected by the configured rejection filter set. note frame id filtering and message id filtering can be enabled/disabled independently of each ot her by setting the masks and values appropriately: mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 160 freescale semiconductor to disable frame id filtering, set the frame id value to 0x0000 and the frame id mask to 0xffff. (no sema ntically valid frame id will be rejected.) to disable message id filtering, set the message id mask to 0x0000 (all message ids are accepted). 3.5 message buffer handling and operations 3.5.1 introduction the flexray mfr4200 uses a partial double buffering t echnique to provide a scheme for buffer handling. using this technology, buffers can be configured as singl e/double transmit message bu ffers, or partially, as single and as double transmit message buffers, as re quired by the application. at the same time, the flexray mfr4200 offers enhanced: active window mechanism interrupt service buffer access scheme the new buffer handling and operations scheme has the following features. the host and the cc have independent access to all the buffers. therefore, the host can access receive/transmit message buffers almost instantly while th e cc transmits/receives frames. the host can configure receive/transmit buffers in the configuration state and partially, during normal operation (see section 3.5.5, ?buffer reconfiguration in the normal state of operation ?). the buffer configuration map is flexible. the buffer mechanism supports multiple locking/un locking of the same transmit buffer, without committing for transmission. the host can commit a tr ansmit message buffer for transmission without update or with only partial update of its data fields. the host explicitly controls every transmit buffer co mmitment for transmission. the host can access a rece ive message buffer while the cc receives a new frame for that buffer. all features are described in more detail in the following sections. 3.5.2 buffer map the flexray cc memory map including buffers locations is shown in table 3-1 . the host accesses cc internal buffer data, configuration, and status fiel ds only through appropriate active receive/ transmit/fifo mess age buffers by using the locking mechan ism. shadow receive message buffers serve the host accesses to message buffers while the cc cont inues to receiv e/transmit frames. message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 161 3.5.3 active message buffers the concept of active message buffers simplifies buffer access fo r the host. if a buffer is locked by the host, then, depending on the message buffer configuration, the buffer data and configuration information is mirrored to one of the active buffers ? the active receive message buffer, the active transmit message buffer, or the active receive fifo buffer. 3.5.3.1 active receive message buffer the active receive me ssage buffer (see table 3-1 ) contains receive message bu ffer data and configuration fields. any receive message buffer is accessible through the act ive receive message buffer after the locking procedure for this buffer has been finished. the active receive message buffer layout is shown in table 3-11 . buffer control, configuration, filteri ng and status data is stor ed in the buffer control, configuration, status and filtering registers set. the la yout of the set is presented in figure 3-131 . figure 3-131. buffer control, configuration, status/filtering register set for transmit/receive buffers buffer control, configuration, status and filtering registers set 472 bytes (4 words x 59 buffers) message buffer 0 cycle counter filter 0 register (ccf0r) message buffer control, configuration and status register (bufcs0r) message buffer 58 cycle counter filter 0 register (ccf58r) message buffer control, configuration and status register (bufcs58r) ... ... ... mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 162 freescale semiconductor note figure 3-131 does not apply to message buffer s configured as receive fifo buffers. 3.5.3.2 active transmit message buffer the active transmit message buffer (see table 3-1 ) contains transmit message buffer data and configuration fields. any transmit message buffer is accessible through the active transm it message buffer after the buffer has been locked successfully. the active transmit message buffer layout is shown in table 3-13 . buffer control, configuration, filteri ng and status data is stor ed in the buffer control, configuration, status and filtering registers set. the la yout of the set is presented in figure 3-131 . 3.5.3.3 active receive fifo buffer the active receive fifo message buffer (see table 3-1 ) contains receive fifo buffer data and configuration fields. any receive fifo buffer is accessible through the acti ve receive fifo buffer after the locking procedure for this buffer has been finished. for a detailed description of fifo access, refer to section 3.6, ?receive fifo function ?. the active receive fifo buffer layout is shown in table 3-12 . the locking procedure for receive fifo buffers is different from the receive/transmit message buffer locking operation (see section 3.5.3.4, ?active buffers locking/unlocking and locking timing ? and the lock bit description in section 3.2.3.7.2, ?message buffer control, configuration and st atus n register, n = [0:58] (bufcsnr) ?). note figure 3-131 is applicable for transmit a nd receive message buffers only, not for receive fifo buffers. if a buffer is configured as a receive fifo buffer, only its buffer control, configur ation and status register (bufcsnr) is used; the ccfnr regi sters are not. instead of the ccfnr registers, the fifo acceptance filter registers and fifo rejecti on filter registers must be used. the buffer control, configuration, st atus and filtering register set for the receive fifo buffers is shown on the figure 3-132 . buffer 0 is configured as a receive fifo buffer. message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 163 figure 3-132. buffer control, configuration, status /filtering register set for receive fifo buffers buffer 0 is configured as a receive fifo buffer; the remaining buffers are configured as receive or transmit message buffers. 3.5.3.4 active buffers locking/ unlocking and locking timing the host accesses any buffer through the active buff ers by using the locking/unlocking mechanism. the lock bit serves as locking requ est (control data) and acknowledgement (status data) at the same time (hence, the host write and read operations to that bit return different values). for a detailed description of the lock bit, refer to section 3.4, ?message buffer control, confi guration, status and filtering register set ?. locking/unlocking procedure: 1. the host sends a message buffer lock request by writing ?1? to the appropriate lock bit of the message buffer in the bufcsnr register (see section 3.4.1, ?message buffer control, configuration and status register ?). buffer control, configuration, status and filtering registers set 472 bytes (4 words x 59 buffers) message buffer 0 ? configured as a receive fifo buffer not used message buffer control, configuration and status register (bufcs0r) message buffer 58 cycle counter filter 0 register (ccf58r) message buffer control, configuration and status register (bufcs58r) ... ... ... mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 164 freescale semiconductor 2. the host checks that the message buffer is lock ed (accessible through an act ive buffer) by reading the lock bit. if the resulting value is ?1?, the message buffer was locked successfully. otherwise, the message buffer could not be locked and the lock request must be repeated. 3. at the same time, the host checks for a locking er ror by reading the lock interrupt flag chierrif in the interrupt status register isr0 (see section 3.2.3.6.6, ?interrupt st atus register 0 (isr0) ?). 4. in the event of a locking error, the hos t may determine the cause of the error (see section 3.2.3.6.3, ?chi error register (chier) ?), and may retry, if necessary. 5. depending on the message buffer type, the host pe rforms buffer read or read/write operations when the message buffer becomes available through an active buffer (lock = ?1?). all transmit message buffers are accessible th rough the active transmit me ssage buffer, receive message buffers through the active receive message buffer , and fifo buffers through the active receive fifo buffer. once the message buffer is lo cked, the host accesses it wi thout checking the lock bit. 6. when the host has finished the message buffer update, it can unlock the message buffer by writing again ?1? to the lock bit. this request to unloc k the message buffer is always and immediately granted, so the host does not have to check the state of the lock bit. 7. the host can start a locking pro cedure for another message buffer. locking principles: the host accesses the fifo, receive message buff ers, and transmit mess age buffers only through the active receive fifo buffer, the active receiv e message buffer, and the active transmit message buffer. the host must lock a buffer, to make it accessible through an active message buffer. the host must unlock a message buffer when it has finished accessing it. the host cannot access sh adow message buffers. the host cannot lock more than one receive m essage buffer and not more than one transmit message buffer. the host can lock up to three buff ers mirrored to the a ppropriate active buffers at the same time ? one transmit message buffer, one receive message buffer, and one receive fifo buffer. the host may lock and unlock transmit and r eceive message buffers several times before committing them. the host may commit a transmit message buffer for transmission (by setting bufcmt to ?1?) after performing several locking/unlocking proce dures on that buffer before committing. unlocking the buffer in the fifo will move the fifo buffer access pointer to the next buffer in the fifo. therefore, the fifo does not support multiple consecutive locking/unlocking procedures for one fifo buffer. the host cannot lock cc part buffer s of double transmit message buffers. the host can lock only the host part bu ffers of double transmit message buffers. once the buffer is locked, the host ac cesses it without checking the lock bit. message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 165 locking errors: refer to section 3.2.3.6.3, ?chi error register (chier) ? for a detailed description. the most important points are as follows. if the controller receives two frames for a receive message buffer that is locked by the host, the controller discards the older frame and sets th e frame lost error fle in the chier register. a message buffer committed for transmission (its bufcmt bit is ?1 ?) cannot be locked. if the host sends a lock request for the committed transm it message buffer, a lock error is raised. the host cannot access the odd buffers (cc part buffer s) of the double transmit message buffers. if it sends a locking request for any odd buffer of a double transmit message buffer, a lock error is raised. if the host tries to lock a second transmit or receive buff er or a second fifo buffer, the controller issues a lock error. see the descripti on of the rble, tble, fble bits in section 3.2.3.6.3, ?chi error register (chier) ?. note the host can write the bufc mt bit of a message buffer only after the buffer is locked and available through an activ e buffer. the bufcmt bit is part of the message buffer control, conf iguration, and status registers bufcsnr[0:58] (see section 3.4.1, ?message buffer control, configuration and status register ?). locking timing: if a transmit message buffer (singl e or double) was committed for transm ission in slot n and unlocked by the host, and if the cc has sch eduled this buffer for tran smission in slot n, then this buffer is locked by the cc for transmission (see the bb bit description in section 3.2.3.6.3, ?chi error register (chier) ?) for the time shown in figure 3-133 . figure 3-133. buffer busy bit timing for a transmit message buffer slot n slot n-1 nit communication cycle tx buffer locking (slot id = n) locking impossible 1 locking possible locking possible 4 t 4 t 1 if the host issues a lock request here, the cc d oes not grant the lock request, but sets the bb flag in the chier register indicating a transmit message buffer busy lock error. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 166 freescale semiconductor 3.5.4 buffer configuration for the cc to start up correctly, the host must configure all the used buffers during the configuration state. the host can reconfigure buffers pa rtially during normal operation (see section 3.5.5, ?buffer reconfiguration in the normal state of operation ?). an example of buffer c onfiguration is presented in figure 3-134 . each buffer is one of following: receive fifo buffer receive message buffer single transmit message buffer double transmit message buffer each double transmit message buffer consists of two pa rts ? the host part buffer and the cc part buffer. the host part buffer of a double transmit message buffer is a buffer with an ev en number configured as a double transmit message buffer. the cc part buffer of a double transmit message buffer is a bu ffer with the next (aft er the host part buffer) number. the accessibility of buffer fields depends on the buff er configuration. all inform ation about buffer field accessibility is summarized in table 3-16 . message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 167 where table 3-16. cc buffer fields accessibility field receive message buffer receive fifo buffer single transmit message buffer for static segment single transmit message buffer for dynamic segment host part buffer of a double transmit message buffer buffer r* ro ro ro_no/wr_cs wr ro_no/wr_cs pp ro ro ro_no/wr_cs wr ro_no/wr_cs nfi ro ro nu nu nu sync ro ro nu nu nu startup ro ro nu nu nu frame id ro_no/wr_cs ro ro_no/wr_cs wr ro_no/wr_cs cycle counter ro ro nu nu nu payload length ro ro ro_no/wr_cs wr ro_no/wr_cs header crc ro ro ro_no/wr_cs wr ro_no/wr_cs data ro ro wr wr wr message buffer slot status vector ro ro ro ro ro cfg ro_no/wr_cs nu ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs iflg ro nu ro ro ro iena wr nu wr wr wr lock wr wr wr wr wr bufcmt nu nu wr wr wr cha ro_no/wr_cs nu ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs chb ro_no/wr_cs nu ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs datupd ro_no/wr_cs nu nu nu nu bt nu nu ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs ccfe ro_no/wr_cs nu ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs tt nu nu ro_no/wr_cs wr ro_no/wr_cs valid ro_no/wr_cs nu ro ro ro cycle counter mask ro_no/wr_cs nu ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs cycle counter value ro_no/wr_cs nu ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs ro_no/wr_cs field with host read-only access during normal operation. host write access only in configuration state ro field with host read-only access wr field with host read/write access nu not used (always hold fixed value ? ?0?). fields with host read access only mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 168 freescale semiconductor configuration procedure during configuration state 1. the cc enters the configuration mode after a hard reset or by th e config bit in the mcr0 register being set (see section 3.2.3.2.1, ?module configur ation register 0 (mcr0) ?). after a hard reset, all message buffers are initialized to as receive message buffers disabled for receive operations (frame id=0x0). all the bits in th e bufcsnr registers are initialized to 0; the frame id fields and ccfnr are cleared (to 0). 2. after the cc has entered the configuration st ate, the host configures a message buffer: ? the host configures the bufcsnr register (c fg, iena, cha, chb, bt , ccfe, and tt bits) (see section 3.4.1, ?message buffer control, configuration and status register ?). ? the host configures the ccfnr register of the message buffer. ? the host locks a message bu ffer in accordance with section 3.5.3.4, ?active buffers locking/unlocking and locking timing ?. ? after the message buffer is locked, the host conf igures the remaining confi guration fields of the message buffer in accordance with th e configuration principles (see below). ? the host unlocks the message buffer. 3. after the host has configured the message buffers, it requests the cc to leave the configuration state by setting the config bit in the mcr0 register to ?0?. c onfiguration becomes active after the cc leaves the configuration state. 4. after the cc leaves the configuration state, it goes to the normal mode of operation (see section 3.9, ?communicatio n controller states ?). note after leaving the hard reset state (the hard reset signal is negated), on the next rising edge of the cc_clk signal, the cc starts performing an internal initialization procedure (see section 3.9.1, ?hard reset state ? and section 3.2.3.1.3, ?magic number register (mnr) ?). during this internal initialization pr ocedure, the cc initializes its inte rnal memory, including the following message buffer configura tion/control parameters. frame id = 0x0 ccfnr: cycle count mask and cycle counter value fields = ?0?s bufcsnr: ? bufcmt = 0 ? cha,chb = 0 ?bt= 0 ? ccfe = 0 ? tt = 0 ? lock = 0 ?iflg = 0 ?valid = 0 ?iena = 0 message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 169 ?cfg = 0 ?datupd = 0 during the internal initialization procedure, the host must not access any cc re gisters except mnr (see section 3.2.3.1.3, ?magic number register (mnr) ?), which acknowledges the finish of the internal initialization procedure. message buffer configuration principles after a hard reset, all message buffers are initia lized as receive message bu ffers disabled for receive operations (frame id=0x0). in nor mal operation, any buffers not conf igured by the host, during the configuration state, remain receive mes sage buffers disabled for receive operations. if a configuration includes fifo buffers (see section 3.2.3.7.1, ?fifo si ze register (fsizr) ?), the fifo starts from message buffer 0 (see figure 3-134 ). buffers of different types can be mixed in the buffer map (recei ve, single transmit, double transmit, and transmit/receive message buffers that are no t used for transmit/receive operations (frame id=0x0)) (see figure 3-134 ). fifo buffers: ? must be placed in a continuous subset of message buffers that is uninterrupted by buffers of other types ? the number of message buffers reserved for the fifo is determined by the fifo size register value (see section 3.2.3.7.1, ?fifo size register (fsizr) ?) the host part buffer of a double transmit message buffer must have an odd number. the number of the cc part buffer of a double tran smit message buffer must be its host part buffer + 1. during the configuration state, only the host part buffer of a doubl e transmit message buffer is available for host read/write conf iguration operations. hence, the hos t part buffer configuration is used for both parts of a double transmit message bu ffer. the configuration of the host part buffer overwrites the configuration of the cc part buffer. only transmit message buffers can be c onfigured as double transmit message buffers. fifo and receive message buff ers are always single buffers. cc part buffers of double transmit message buff ers have read-only host access. cc part buffers cannot be locked; consequently, the host can read only the bufcsnr and ccfnr registers of the buffer. an example of buffer configuration is presented in figure 3-134 . mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 170 freescale semiconductor figure 3-134. example of a buffer configuration 3.5.4.1 receive message buffer configuration receive message buffers can be confi gured in the configurat ion state. the configur ation must be done in accordance with the configuration procedure and prin ciples. the cfg bits in the bufcsnr of receive message buffers are 0. the number of receive mess age buffers is configurable; however, receive message buffer s cannot be placed between fifo buffers or between the host and cc parts of double transmit m essage buffers. receive message buffers cannot be double message buffers. buffer 0 buffer 1 buffer 2 buffer 3 buffer 4 buffer 5 buffer 6 buffer 7 buffer 8 buffer 10 buffer 9 buffer 11 buffer 13 buffer 15 buffer 17 buffer 19 buffer 53 buffer 55 buffer 57 buffer 12 buffer 14 buffer 16 buffer 18 buffer 52 buffer 54 buffer 56 buffer buffer buffer buffer - receive fifo buffer - receive message buffer - transmit message buffer (dynamic segment) - transmit message buffer (static segment) buffer buffer buffer - single buffer - double buffer host can reconfigure those buffers during normal mode of operation host cannot reconfigure the fifo size during normal mode of operation buffer 58 ? ... message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 171 it is possible to configure from 0 to 59 buffers as receive message buffers. 3.5.4.2 transmit message buffer configuration transmit message buffers can be configured in the c onfiguration state. single tra nsmit message buffers for the dynamic segment can be configured in the c onfiguration state and during normal operation. the configuration must be done in accor dance with the configur ation procedure and prin ciples. the cfg bits in the bufcsnr of transmit message buffers are 1?s. the number of transmit message buffers is configurab le; however, transmit message buffers cannot be placed between fifo buffers or be tween the host and cc parts of double transmit message buffers. transmit message buffers can be conf igured as single or double transmit message buffers for static and dynamic segments. if a message buffer is part of a double transmit message buffer: the host part buffer must be an even number buffer only. the cc part buffer must be an odd number buffer only. the number of the cc part buffer must be its host part buffer number + 1. the host must set only a host part buffers configur ation in the configurati on state. cc part buffers of double transmit message buffers will be initialized by the sam e configuration automatically. in normal mode of operation host ope rates only with the host part buff ers control and status fields. it has read-only accesses to the cc part buffers control and status fields (see section 3.4.1, ?message buffer control, conf iguration and status register ?). it is possible to configure from 0 to 59 message bu ffers as single transmit me ssage buffers, or 29 double transmit message buffers, or different mixtures of single and double transmi t message buffers (for example, 15 single transmit message buffer s + 22 double transmit message buffers). 3.5.4.3 receive fifo configuration fifo receive buffers can be configured only in the c onfiguration state. first, the host must set the fifo size register (see section 3.2.3.7.1, ?fifo size register (fsizr) ?). note the fifo is configured only via the fsizr register. the host can write the fifo size re gister only during the configuration state. the configuration must be done in accordance with the confi guration procedure and principles. if a configuration includes fifo buffers, message buffer 0 must be the first fifo buffer (see figure 3-134 ). the subset of fifo buffers must be contiguous. it is possible to configure up to 59 messag e buffers as fifo receive message buffers. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 172 freescale semiconductor 3.5.5 buffer reconfiguration in the normal state of operation reconfiguration procedure during the normal state of operation: the host must follow the configurat ion principles and procedure as we ll as reconfiguration principles, while reconfigures the message buffers during normal operation. reconfiguration principles: 1. only single transmit message buffers for dynamic segment (st bds) are reconfigurable in normal operation. 2. states and parameters that are reconfigurable: ? parameters of stbds accessible for host w rite operations (see section , ?receive, receive fifo, and transmit message buffers are acc essible to the host mcu only through the active receive, active transmit, and ac tive receive fifo buffers. ? and section 3.4.1, ?message buffer control, configuration and status register ?). 3. buffers, states and parameters that are not reconfigurable: ? fifo size ? double transmit message buffers ? receive message buffers ? buffers from transmit message buffers to receive message buffers, and vice versa ? all the filtering parameters (channel filter s configuration, frame id filters configuration (except single transmit message buffers for dynamic segment), mess age id filters configuration and masks, message buffer filtering configuration) ? buffers cannot be reassigned from stat ic to dynamic segment, or vice versa. ?fifo ? buffers cannot be reconfigured from single to double transmit message buffers, or vice versa. ? buffers assigned to the static segment are not reconfigurable figure 3-135 shows how cc buffers can be configured and re configured during the co nfiguration state, and reconfigured during the normal state of the cc: message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 173 figure 3-135. transition scheme between different buffer types depending on operational mode of cc 3.5.6 message buffer operations the main principles of the host and the cc data exchange are as follows. the host has full control over the cc. after the configuration step is performed by th e host, the cc can run the flexray protocol. the cc does not require any additional support from the host for operation in a cluster without faults and disturbances. data exchange is based on access requests and acknowledge flags. the host and the cc provide a set of transmit/receive operations fo r managing data flow between a flexray network and the host. 3.5.6.1 data collection during receive operation frames are stored in the chi if there is at least one receive message buffer or fifo receive buffer configured. therefore, it actively participates in th e internal buffer filters matching process, which takes single/double transmit message buffer, static segment single transmit message buffer, dynamic segment receive message buffer transition in the normal and in the configuration states transition in the configuration state double transmit message buffer, dynamic segment mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 174 freescale semiconductor place every time the communication cont roller receives a semantically valid and syntactically correct frame. an example of operations during a frame reception is shown on the figure 3-136 . 3.5.6.1.1 the host op erations during reception after every successful frame recepti on, the cc sets the flag iflg of a matc hing buffer. this flag indicates that a frame has been received and stored in a buffer , and the host can read it to empty the buffer for the next reception. all iflg b its are logically or?ed and connected to the host interrupt line. the host receives an interrupt if at least one iflg is set and not masked by the appropriate iena bit in the bufcsnr register. to read a receive message buffer the host must perform the following steps: 1. process an interrupt by reading the isr registers, if necessary. or check the iflg bits of receive message buffers. 2. locate one iflg interr upt source register by reading the recei ve message buffer interrupt vector register (see section 3.2.3.6, ?interrupt and error signalin g related status registers ?). 3. send a lock request (write lock bit with the va lue ?1?) for the corresponding message buffer, to make it accessible through the active receive message buffer. 4. wait for lock acknowledge (lock bit reads as value ?1?). 5. read the active receive message buffer. 6. send an unlock request for the message buffer. message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 175 figure 3-136. operations during a frame reception data0 0 1 iflg lock 1 host operations receive message buffer a shadow buffer cc received a new message for buffer a updated the buffer . . ... buffer is locked new frame reception cc operations data0 1 1 iflg lock 1 data1 reception data0 1 1 iflg lock 1 data1 reception data0 1 1 iflg lock 1 data1 reception data0 0 0 iflg lock 1 data1 data0 0 1 iflg lock 1 cc starts reception of a new message that matches the filtering conditions of buffer a after at least one communication cycle cc continues reception of the new message cc received the new semantically valid frame cc in the shadow buffer with buffer a cc continues reception of the new message ... host receives an iflg interrupt and locks the buffer by sending a lock request (writes ?1? to the lock bit) and checking the acknowledge lock 1 bit buffer is locked by host and performs read/write operation with the buffer buffer is still locked by host and performs read/write operation with the buffer buffer is still locked by host. it has finished read/write operation with the buffer and unlocks it by sending an unlock request (writes ?1? again to the lock bit. buffer is unlocked and iflg is reset to ?0? . . host receives an iflg interrupt time . . note: 1 read back value of the bit. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 176 freescale semiconductor 3.5.6.1.2 cc operatio ns during reception the cc receives every frame to a shadow message buffer first, as shown in figure 3-136 . note a frame received in slot n and stored in a configured message buffer or fifo is accessible to the host, through the chi , 16 t after the start of slot n+1. the cc performs a filtering process based on filter configur ation. this process tak es place every time the cc receives a semantically valid and syntactically correct frame. in th is process, the cc sequentially compares all the receive message buffers filters to the received ones. the first m essage buffer matching all the filtering requirements will be updated with the new frame. the matching message buffer will be overwritten, if the message buffer wa s already full (iflg = 1). if a received frame does not match the filtering fields of any receive message buffer, it will be compared with th e fifo filters. if a frame matches the fifo filtering parameters , it will be stored in the fifo; otherwise, it will be ignored. the cc ignores invalid frames and does not store them in buffers. the received frame will be stored in the first matching receive message buffer. the search engine starts after the end of the fifo, or at message buffer 0 (if no fifo is configured), and searches upwards. thus, if there are two receive message buffers matching the received frame, the frame will always be stored in the buffer with the lower buffer index. the cc does not check which buffer fits the frame best. thus, if a message buffer holds a filtering subs et of another message buffer, that message buffer (with the filtering subset) must be located at the lower message bu ffer index. the application must manage this. the matching message buffer will not be updated if it is still locked. if the message buffer is locked after reception, it will be updated as soon as it is unlocke d. if the buffer is locked for more than one communication cycle and, if the frame, which matches that message buffer filte ring, is received twice during this period, the buffer will be updated with the newer frame, as soon as it is unlocked, and a frame lost error will be raised to the host (see section 3.2.3.6.3, ?chi error register (chier) ?). the corresponding iflg bit (message buffer is full) is set every time the message buffer is updated, and, if enabled, a receive in terrupt is generated. in the case of locking, when the host may lock one receive message buffer, the cc has two shadow message buffers per channel to continue frame reception targ eted for any receive mess age buffers including the locked one. note during the filtering process, the cc mu st check the payload length field of a received frame before the cc applies message id filteri ng. if the payload length of a received frame is too small to hold the full message id value, the cc performs the message id filteri ng with the default message id value (0x0). 3.5.6.2 data collection during transmit operation some or all of the message buffers can be confi gured as transmit message buffers via the bufcsnr register sets (see section 3.4.1, ?message buffer control, configuration and status register ?). the configuration of transmit message buffers must comply with the bu ffer configuration procedure and message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 177 principles. the cc handles transm it operations differently during the static and dynamic segments of transmission; it also handles single and double transmit message buffers differently. for transmission, the cc uses data from configured and co mmitted transmit message buffers only. the host submits a frame for transmission by co mmitting a message buffer for transmission (bufcmt bit) and by subsequent unlocking of the transmit m essage buffer. the transmit message buffer remains valid for transmission until its valid bit = 1. to prepare a transmit message buffer for transm ission, the following steps must be performed. 1. configure the message buffer as a transmit m essage buffer in accordance with the buffer configuration procedure and principles. 2. lock the corresponding message buffer, to make it accessible in the ac tive transmit message buffer. buffer locking must be done in accorda nce with the locking/unl ocking procedure and principles 3. write/read the active transmit message buffer to change or update the message buffer content. 4. commit the message buffer for transmission, by setting the bufcmt bit to ?1?. 5. unlock the message buffer. commitment-to-transmission time for single and double transmit message buffers: to transmit a frame in slot n, the hos t must commit and unlock the buffer: static segment transmit message buffer: 4 t before the beginning of slot n-1 or the network idle time (nit). dynamic segment transmit message buffer: 4 t befo re the beginning of slot n-1 or the network idle time (nit). static segment: for the static segment, if there are several fr ames pending for transmission, the frame with the id corresponding to the next sending slot is selected for transmission. the cc checks other filtering fields of those messages. if several frames ar e suitable for current static slot transmission, the cc performs an internal arbitration. the cc transmission procedure is described in detail in the frame processing section of the pwd. the most important points are as follows. only valid frames (valid bit = 1) can be transmitted by the cc. if there are valid frames with th e same frame id, the cc checks thei r filter fields. if two or more of them match the conditions of the transmit sl ot, the message buffer with the lowest message buffer number wins the internal arbitration. if two buffers are assigned to the same static slot but to different transmission channels, the cc transmits them simultaneously on assigned channels during transmission of that static slot. if a message buffer was committed for transmi ssion (bufcmt = 1) it becomes valid (valid = 1) after buffer unlock operation, and the host cannot lock it until it is transmitted at least once. the cc changes the following bits, if a mes sage from a message buffer has been sent. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 178 freescale semiconductor iflg bufcmt valid (depending on the tt bit of the bufcsnr register ? see section 3.4.1, ?message buffer control, configuration and status register ) dynamic segment in the dynamic segment, if several valid frames are pending within the in terface, the frame with the highest priority (lowest frame id) is selected next. the cc transmission procedure is described in deta il in the frame processing section of the pwd document. the most important points are as follows. in the dynamic segment, different minislot seque nces are possible on both channels (concurrent sending of different idx on both channels). pending frames are selected in acco rdance with their identifier and their filter configuration. frames overlapping with the network idle time (nit), defined by the nitcr (see section 3.2.3.3.18, ?network idle time configuration register (nitcr) ?), will be not transmitted. if there are two or more transmit message buffers with the same iden tifier, the message buffer with the lowest number wins the internal arbitrati on and will be transmitte d; the remaining message buffer(s) with matching filters will be rem oved from the arbitration process until the next communication cycle. if a message buffer was committ ed for transmission (bufcmt= 1) it becomes valid (valid = 1) after the buffer unlock operation. the host cannot lo ck it until it is transmitted; this prevents changing of a message buffer?s fields, wh ile it is waiting to be transmitted. only valid frames (valid bit = 1) can be transmitted by the cc. only identifiers that are higher than the highest static identifier are allowed for the dynamic segment. if there are valid frames with th e same frame id, the cc must chec k their filter fields. if two or more of them match the conditions of the transmit slot, the message buffer with the lowest address wins the internal arbitration. the cc does not transmit null frames in the dynamic segment. if two message buffers are assigne d to the same dynamic slot but to different transmission channels, the cc transmits them on the same minislot num ber and assigned channels during transmission of that dynamic slot. the cc changes the following bits if the message buffer has been sent. 1. iflg 2. bufcmt 3. valid (depending on the tt bit of the bufcsnr register ? see section 3.4.1, ?message buffer control, configuration and status register ) message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 179 3.5.6.2.1 single transmit messa ge buffer data collecti on during transmit operation the host can configure some message buffers of the cc as single transmit message buffers. if there is at least one transmit message buffer configure d, or the sync frame register value (see section 3.2.3.3.29, ?sync frame register (syncfr) ?) is not 0x0, the cc can actively transmit frames out of the connected flexray network. to configure a single transmit message buffer, the following next steps must be performed. 1. configure the message buffer as a transmit message buffer, in a ccordance with the configuration procedure and principles. 2. set the message buffer type bit (bt) to 0 ? single transmit message buffer. after a buffer is configured as a single transmit message buffer and a cc enters the normal mode of operation, the host can start pr eparation and commitment of frames for transmission. figure 3-137 shows an example of host and cc operation on a single tr ansmit message buffer during frame transmission in normal operation. as shown in figure 3-137 , the host sends a lock request for a message buffer and always checks for the lock request acknowledge bit lock to be a ?1? before it starts to upda te the message buffer content (see section 3.5.3.4, ?active buffers locking/unlocking and locking timing ? and section 3.2.3.6.3, ?chi error register (chier) ? for more information). after a transmit message buffer is lo cked, the host can update it, via the active transmit message buffer, and can commit it to transmission by setting the bu fcmt bit to ?1? and unlocking the message buffer. after transmission, the cc sets the iflg bit of a message buffer, and clears bufcmt. the cc changes the valid bit after transmis sion depending on the tt bit. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 180 freescale semiconductor figure 3-137. operations with a single transmit message buffer during an event type of transmission for a static segment data1 0110 valid iflg lock 1 bufcmt data1 0111 valid iflg lock 1 bufcmt data1 1011 valid iflg lock 1 bufcmt data1 1001 valid iflg lock 1 bufcmt data1 1001 valid iflg lock 1 bufcmt data1 1001 valid iflg lock 1 bufcmt data1 0110 valid iflg lock 1 bufcmt data2 1011 valid iflg lock 1 bufcmt data2 0111 valid iflg lock 1 bufcmt host operations transmit message buffer with frame id = a cc operations lock request (host writes lock=1) unlock request (host writes lock=1) lock request (host writes lock=1) lock request (host writes lock=1) unlock request (host writes lock = 1) but access not granted because cc locked the buffer. lock request (host writes lock=1) but access not granted because cc locked the buffer. cc transmission request. access granted cc transmission on request. access not granted because host locked the buffer cc transmits a null frame because the buffer is locked by host and there is no other matching buffer cc transmits data1 transmission done transmission done ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... host updates data and commits buffer for transmission host updates data and commits buffer for transmission transmission of data1 transmission of null frame time note: 1 read back value of the bit. message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 181 3.5.6.2.2 doubled buffer data co llection during transmit operation the host can configure some message bu ffers of the cc as double transmit message buffers. if there is at least one double transmit message buffer configured, then the cc can activ ely transmit frames out of the connected flexray network. to configure a double transmit message buffer ( figure 3-138 ), the follow steps must be performed. 1. configure the even number message buffer as a transmit message buffer, in accordance with the configuration procedure and principles. 2. set the message buffer type bit bt (see section 3.4.1, ?message buffer control, configuration and status register ?) to 1 ? host part buffer of double tra nsmit message buffer s (configuration is copied to the cc part buffers automatically). the figure 3-139 shows an example of a double transmit me ssage buffer data collection during the state driven transmit operation in normal operation. the figure 3-140 shows an example of a doubled transmit messa ge buffer data collection during the event driven transmit operation. note when the cc transmits a null frame, it does not change the bufcsnr registers of the buffers. host operations with a double transmit message buffer during transmission the host can perform the following operati ons on a double transmit message buffer. lock buffer for reading and/or modifying. read message buffer slot status vector, data and configuration. write data. commit and unlock for transmission. main principles of the host operations with double transmit message buffers: the host always operates with host part buffers. the host can perform operations with host part buff ers independent of cc tr ansmit operations from the cc part buffers. data exchange is based on access requests and acknowledge flags. the host and the cc operate only with configured buffers that have frame id field not equal to ?0?. the addresses of the host part buffer s do not change during normal operation. the host has read-only access to the cc part buffer bufcsnr registers. buffer number (even) host part buffer n buffer number+1 (odd) cc part buffer n+1 bufcs(n) bufcs(n+1) figure 3-138. double transmit message buffer structure mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 182 freescale semiconductor the host operates with a double tran smit message buffer in the same way as it does with a single transmit message buffer. the host can receive an iflg interrupt after transmission of a committed cc part buffer. the host cannot lock a host part buffer (read value of the lock= 0) during swap and copy procedures. the host part buffer of a double tr ansmit message buffer cannot be locked (read back value of the lock= 0), if the host has commit ted the host part buffer for tran smission but the bufcmt bit of the cc part buffer is still ?1? (a frame has not yet been transmitted). if the host has committed a host part buffer of a double message buffer for transmission, the cc performs an atomic swap of th e host part and cc part buffers in cluding the bufcsnr registers of the host and the cc part buffers, and starts a copy process. cc operations with a double transmit message buffer during transmission the cc performs the following operatio ns on a double transmit message buffer. 1. lock buffer for transmission. 2. update the message buffer slot status v ector of the host and the cc part buffers. 3. swap host and cc part buffers after commitment for transmission. 4. copy the cc part buffer to the host part bu ffer during commitment for transmission. the cc copies the following fields from a cc part buffer of a double transmit buffer to a host part buffer (see section 3.5, ?message buffer handling and operations ?): ?r* ?pp ? frame id ? payload length ? header crc ? data[0:31] ? message buffer slot status vector main principles of cc operations with double transmit buffers: the cc may perform transmit operations from th e cc part buffers whil e the host updates the host part buffers. data exchange is based on access requests and acknowledge flags. the host and the cc operate only with configured buff ers that have frame id fields not equal to ?0?. the numbers of the cc part buffer s do not change during normal operation. as it is presented in section 3.5.6, ?message buffer operations ?, host operations on a host part of a double transmit message buffer are the same as they are on a single transmit message buffer. however, cc operations with host part and cc part buffers are different. message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 183 table 3-17. double transmit message buffer data collection with state driven transmit operation time point host operatio ns cc operations 1 the host sends a lock request to a host part buffer of a double transmit message buffer (it writes lock=?1?) and receives a request acknowledge (read back value of the lock=?1?). ? 2 the host part buffer is locked. the host updates the buffer contents. the cc starts frames transmission and sends a buffer lock request for cc part buffer to transmit the frame this buffer holds. 3 the host part buffer is locked. the host updates the buffer contents. the cc locked the cc part buffer and transmits the frame from it 4 the host part buffer is locked. the host finished data update (buffer holds the data1), committed the buffer for transmission (bufcmt=?1?) and sent an unlock request (it writes again lock=?1?) the cc finished transmission and updates the bufcmt, valid and iflg bits of the cc part buffer 5 unlock granted. the cc clears the iflg bit of the host part buffer to ?0? and sets the valid bit. the cc perfor ms an atomic swap of the host part and cc part buffers including the bufcsnr registers and starts a copy process. 6 ? the atomic swap of the host part and cc part buffers is done. the cc starts the copy process from the new cc part buffer to the host part buffer. bufcmt bit of the host part buffer is ?1? until those processes are finished (the host cannot lock the host part buffer). 7 ? the cc continues the copy process and starts frames transmission. the cc sends a buffer lock request for cc part buffer to transmit the frame this buffer holds. 8 the host sends a lock request to a host part buffer of a double transmit message buffer (it writes lock=?1?) but does not receive a lock request acknowledge (read back value of the lock=?0?) due to the copy process running. the cc continues the copy process.the cc locked the cc part buffer and transmits the frame from it. 9 ? the cc transmits the frame from the cc part buffer. the cc finished the copy process (the host can lock the buffer). 10 the host sends a lock request to a host part buffer of a double transmit message buffer (it writes lock=?1?) and receives a request acknowledge (read back value of the lock=?1?) and has starts to update data in the host part buffer. the cc transmits the frame from the cc part buffer. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 184 freescale semiconductor figure 3-139. doubled buffer data collection with state driven transmit operation data0 0110 valid iflg lock 1 bufcmt host operations cc operations lock request (host writes lock=1) cc transmission request host updates data and commits buffer for transmission data0 11 0 valid iflg bufcmt data0 0110 valid iflg lock 1 bufcmt 11 0 valid iflg bufcmt 0110 valid iflg lock 1 bufcmt unlock request (host writes lock=1) 11 0 valid iflg bufcmt data1 0110 valid iflg lock 1 bufcmt data0 11 0 valid iflg bufcmt invalid data during 0110 valid iflg lock 1 bufcmt lock request (host writes lock=1) 10 1 valid iflg bufcmt data1 0110 valid iflg lock 1 bufcmt lock request (host writes lock=1) 10 1 valid iflg bufcmt lock not granted host part buffer ? even part of a double buffer (even buffer number) cc part buffer ? odd part of a double buffer (odd buffer number) buffer locked data1 buffer locked copy process for data1 data0 buffer locked by cc data0 buffer locked by cc data1 buffer locked by cc data1 buffer locked by cc copy process swap cc transmits data0 transmission done cc transmission request cc performs atomic swap operation of two buffers cc transmits data0 transmission done host updates data and commits buffer for transmission transmission of data1 cc performs a copy process transmission of data0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... note: 1 read back value of the bit. time 1 10 2 3 4 8 9 5 6 7 message buffer handling and operations mfr4200 data sheet, rev. 0 freescale semiconductor 185 figure 3-140. doubled buffer data collection with event driven transmit operation data0 0110 valid iflg lock 1 bufcmt host operations cc operations lock request (host writes lock=1) host updates data and commits buffer for transmission data0 01 0 valid iflg bufcmt data0 0110 valid iflg lock 1 bufcmt 01 0 valid iflg bufcmt 1111 valid iflg lock 1 bufcmt unlock request (host writes lock=1) 01 0 valid iflg bufcmt data1 1001 valid iflg lock 1 bufcmt data0 01 0 valid iflg bufcmt invalid data during 0100 valid iflg lock 1 bufcmt lock request (host writes lock=1) 10 1 valid iflg bufcmt data1 1110 valid iflg lock 1 bufcmt lock request (host writes lock=1) 10 1 valid iflg bufcmt lock not granted host part buffer ? even part of a double buffer (even buffer number) cc part buffer ? odd part of a double buffer (odd buffer number) buffer locked data1 buffer locked copy process for data1 data0 buffer locked by cc data0 buffer locked by cc data1 buffer locked by cc data1 buffer locked by cc copy process swap cc transmission request cc performs atomic swap operation of two buffers cc transmits data0 transmission done host updates data and commits buffer for transmission transmission of data1 cc performs a copy process ... ... ... ... ... ... ... ... note: 1 read back value of the bit. time 1 10 2 3 4 8 9 5 6 7 mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 186 freescale semiconductor 3.6 receive fifo function some or all of the message buffers can be configur ed as a receive first-in-first-out (fifo) system. the fifo always starts at message buffer 0 and can be configured to a maximum of 59 message message buffers by means of the fifo size register (see section 3.2.3.7.1, ?fifo size register (fsizr) ?). table 3-18. double transmit message buffer data collection with event driven transmit operation time point host operatio ns cc operations 1 the host sends a lock request to a host part buffer of a double transmit message buffer (it writes lock=?1?) and receives a request acknowledge (read back value of the lock=?1?). the valid bit of the cc part buffer is ?0? ? data is not valid and the cc does not transmit frame containing data from this buffer 2 the host part buffer is locked. the host updates the buffer contents. the valid bit of the cc part buffer is ?0? ? data is not valid and the cc does not transmit frame containing data from this buffer 3 the host part buffer is locked. the host updates the buffer contents. the valid bit of the cc part buffer is ?0? ? data is not valid and the cc does not transmit frame containing data from this buffer 4 the host part buffer is locked. the host finished data update (buffer holds the data1) , committed the buffer for transmission (bufcmt=?1?) and sent an unlock request (it writes again lock=?1?) the valid bit of the cc part buffer is ?0? ? data is not valid and the cc does not transmit frame containing data from this buffer 5 unlock granted. the cc clears the iflg bit of the host part buffer to ?0? and sets the valid bit. the cc performs an atomic swap of the host part and cc part buffers including the bufcsnr registers and starts a copy process. 6 ? the atomic swap of the host part and cc part buffers is done. the cc starts the copy process from the new cc part buffer to the host part buffer. bufcmt bit of the host part buffer is ?1? until those processes are finished (the host cannot lock the host part buffer). 7 ? the cc continues the copy process and starts frames transmission. the cc sends a buffer lock request for cc part buffer to transmit the frame this buffer holds. 8 the host sends a lock request to a host part buffer of a double transmit message buffer (it writes lock=?1?) but does not receive a lock request acknowledge (read back value of the lock=?0?) due to the copy process running. the cc continues the copy process.the cc locked the cc part buffer and transmits the frame from it. 9 ? the cc transmits the frame from the cc part buffer. the cc finished the copy process (the host can lock the buffer). 10 the host sends a lock request to a host part buffer of a double transmit message buffer (it writes lock=?1?) and receives a request acknowledge (read back value of the lock=?1?) and has starts to update data in the host part buffer. the cc transmits the frame from the cc part buffer. receive fifo function mfr4200 data sheet, rev. 0 freescale semiconductor 187 every incoming frame not matching any receive filter , but matching the programmable fifo filters, is stored in the fifo buffer system. in this case, the re ceived frame and its message buffer slot status vector are stored in the next fi fo message buffer, including. there are two status bits in is r0 (see the rfneif and rfoif bits in section 3.2.3.6.6, ?interrupt st atus register 0 (isr0) ?): one shows that the receive fifo is not empty; the other shows that a receive fifo overrun has been detected. interrupts are generated, if interrupts are enabled. note the cc does not store null frames and invalid frames in fifo. if the cc has two channels configur ed, then, during the static part of transmission, the cc stores in the fifo first the frame received on channel a, and then the frame received on channel b. all fifo filtering conditions must match for both received frames. there are two internal (not host a ccessible) index registers associate d with each fifo. the put index register (putidx) is used as an index to the next available location in the fifo buffer system. when a new frame is received, it is written into the message buffer addressed by the pu tidx register; the putidx register is then incremented, to address the next me ssage buffer. if the putidx register is incremented past the highest fifo message buffer, the putidx register is reset to 0. the get index register (getidx) is used to address the next fifo buffer to be read. the geti dx register is incremented when unlocking one of the receive fifo buffers. the fifo buffer system is completely filled when the put pointer (putidx) reaches the va lue of the get pointer (getidx). new incoming frames cannot be stored in the fifo. the fifo overrun flag is set at th e end of this frame if no er ror has occurred. a receive fifo non empty status is detected when the putidx register diff ers from the getidx register. this indicates that there is at least one rece ived frame in the fifo buffer system. the putidx register and the getidx re gister cannot be accessed by the host. the fifo empty, fifo not empty, and fifo overrun situations are explained in figure 3-141 . figure 3-141. fifo status (empty, not empty, overrun) ? example of fifo with three message buffers ? ? ? a ? ? a b c 012 012 012 getidx getidx putidx was incremented last + new incoming message (which is lost) (read) (read) getidx (read) fifo empty fifo not empty fifo overrun putidx (write) putidx (write) putidx (write) mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 188 freescale semiconductor to read a receive fifo buffer, the host must lock the fifo buffer by sending a lock request (lock=?1?) to message buffer 0. when a fifo buffer is locked (re ad back value of the lock=?1?), the message buffer addressed by getidx appears in the active receive fifo buffer. after reading, the fifo buffer must be unlocked, and the getidx poi nter is incremented. the complete set of fifo accepta nce/rejection filters consists of the following registers (see section 3.2.3.8, ?filtering related registers ?). two filter sets are available for fifo filtering: one fifo acceptance filter set, comprising: ? fifo acceptance filter message id value register ? fifo acceptance filter message id mask register one fifo rejection filter set, comprising: ? fifo rejection filter frame id value register ? fifo rejection filter frame id mask register the channels from which the received frame will be accepted or re jected by the fifo acceptance/rejection filters are specified in section 3.2.3.8.7, ?fifo accepta nce/rejection filter channel register (fafchr) ?. the fifo acceptance filter value registers define th e acceptable pattern of the frame to be received. the fifo acceptance filter mask registers specify which of the corresponding bits ar e marked ?don?t care? for acceptance filtering. the fifo rejection filter value registers define the ac ceptable pattern of the frame to be rejected. the fifo rejection filter mask registers spec ify which of the corresponding bits ar e marked ?don?t care? for rejection filtering. if acceptance and rejection filter are configured to ma tch the same identifier, the frame will be rejected. note the content of the fifo is not rese t by entering, being in, or leaving the configuration state. therefore, if th e cc has stored any messages in the fifo, and has entered the configur ation state without reading those messages, and has returned to nor mal operation, then those messages will remain in the fifo. the cc automatically updates the bufcsnr registers of the fifo buffers to 0x0 values when the cc en ters the configuration state for the first time. the host must clear buffer control flags cfg, iflg, and iena (write 0x0000 to the buffer control register) of a message buffer that has already been in use or that has alre ady been configure d, before the host may extend the fifo (alter the fifo size) to incl ude that message buffer in the fifo. failing to do so will re sult in invalid indications in the rbivec/tbivec registers (see section 3.2.3.6.1, ?receive buffer interrupt vector register (rbivecr) ? and section 3.2.3.6.2, ?transmit buffer interrupt vector register (tbivecr) ?), i.e. rbivec/tbivec host controller interfaces mfr4200 data sheet, rev. 0 freescale semiconductor 189 will still indicate asserted iflg bits for the m essage buffer that has been included in the fifo. 3.7 host controller interfaces the flexray communicati on controller can be connected and contro lled by two types of microcontrollers through the cc mcu interface. two pins, if_sel0 and if_sel1, configure the interface for the type of mcu. the mcu type is selected by if _sel0 and if_sel1 inputs as shown in table 3-19 . when it leaves the hard reset state, the cc latch es the values of the if_sel 0 and if_sel1 signals and configures the interface for the type of mcu accordi ngly. the cc does not analyze if_sel0 and if_sel1 after it has left the hard reset state (see section 3.9.1, ?hard reset state ?). note if the cc senses the unsupported mode on its if_sel pins, it stops all internal operations, does not perfor m/respond on any host transactions, stays in the configuration mode, and does not integrate into the communication process. the following steps must be taken to select a correct mcu interface mode. 1. if_sel0, if_sel1 must be set to the ami or hcs12 mode. 2. the hard reset signal of th e cc must be asserted again. 3.7.1 mfr4200 asynchronous memory interface the mfr4200 asynchronous memory interface is shown in figure 3-142 . this interface has the following characteristics and features: data exchange in ami mode is contro lled by the ce#, we# and oe# signals. the mfr4200 ami is implemented as an asynchr onous memory slave module, thus enabling fast interfacing between the cc and a variety of microcontrollers. the mfr4200 ami decodes its inte rnal registers addresses with the help of the chip select signal ce# and the address lines a[9:1]. note the address space from 0x0400 to 0x1fff is reserved. readi ng this address space results in data 0x0000, while wr iting will not change the memory. reading or writing this address space will set the illadr bit in chier. table 3-19. flexray cc mcu interface configuration mode if_sel0 if_sel1 unsupported 0 0 hcs12 0 1 ami 1 0 unsupported 1 1 mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 190 freescale semiconductor the ami module accepts only 16-bit wide (word) transactions. it does not have byte select lines and, thus, does not recognize 8-bit wide accesses. therefore, it does not indicate errors in the event of 8-bit transactions. the we# signal indicates the directio n of data transfer for a transaction. the oe# signal enables the ami data output to a microcontroller du ring read transactions. int_cc# is an interrupt line that can be used for requesting, by means of the internal interrupt controller, a service routine from a host controller. the mfr4200 ami module does not support burst transactions. figure 3-142. connecting mfr4200 to mpc5xx using the ami (example) d15 d0 we# ce# to the phy mfr4200 ... a9 a1 ... oe# int_cc# if_sel0/bgt/dbgt if_sel1/txd_bg1/txd_485 ... ... ... ... d0 d15 we# csn# ... a22 a30 ... oe# irqn# to the phy vddio vddio microcontroller mpc5xx host controller interfaces mfr4200 data sheet, rev. 0 freescale semiconductor 191 figure 3-143. connecting mfr4200 to mac71xx using the ami (example) figure 3-144. connecting mfr4200 to dsp56f83x (hawk) using the ami (example) d15 d0 we# ce# to the phy mfr4200 ... a9 a1 ... oe# int_cc# if_sel0/bgt/dbgt if_sel1/txd_bg1/txd_485 ... ... ... ... d15 d0 rd/wr# csn# ... a9 a1 ... oe# irqn# to the phy vddio vddio microcontroller mac71xx d15 d0 we# ce# to the phy mfr4200 ... a9 a0 ... oe# int_cc# if_sel0/bgt/dbgt if_sel1/txd_bg1/txd_485 ... ... ... ... d15 d0 wr# csn# ... a9 a1 ... rd# irqn# to the phy vddio vddio microcontroller dsp56f83x mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 192 freescale semiconductor 3.7.1.1 ami interface signals and pins description where: i ? input pin; o ? output pi n; i/o ? input/output pin 3.7.2 mfr4200 hcs12 interface the mfr4200 hcs12 interface with hcs12 ebi paged mode support is shown in figure 3-145 . the flexray cc to hcs12 connection with hcs12 ebi unpaged mode support is shown in figure 3-146 . the mfr4200 hcs12 interface supports the paged and unpaged modes of the hcs12 external bus interface connected to it. the mfr4200 hcs12 interface is implemented as a synchronous hcs12 external bus slave module, thus enabling fast data exchange between them. the mfr4200 hcs12 interface decodes addresses of read/write transactions to its internal registers and generates its internal cs signal wi th the use of the address/data lines pad[0:15], acs[0:5] and xaddr[14:19] (see figure 3-147 ). ? the address and data lines pad[0:15] are mu ltiplexed. they are denoted adr[0:15] when referring to the address and data[0:15] when referring to the data. the mfr4200 is selected only when the address adr[10:15] matches acs[ 0:5] (adr[10] matc hes acs[0], adr[11] matches acs[1], etc.), and the address xaddr[14:19] matches 0. table 3-20. ami interface signals and pins description signal name mcu external bus and memory controller pin flexray cc mcu interface pin function description name i/o name i/o d[15:0] d[15:0] i/o* d[15:0] i/o data bus , d0 is the lsb of data a[9:1] a[9:1] o a[9:1] i address bus , a1 is the lsb of address rd/wr# rd/wr# o we# i read/write ? indicates the direction of the data transfer for a transaction. a logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. oe# oe# o oe# i output enable signal , controls ami data output during read transactions irqn# irqn# i int_cc# o i nterrupt request (level sensitive) ? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the mpc555. if_sel[0:1] ? ? if_sel[0:1] i interface select ? flexray cc mcu interface configuration pins csn# csn# o ce# i chip select/chip enable ? these signal enable peripheral or memory devices at programmed addresses if defined appropriately in the memory controller. host controller interfaces mfr4200 data sheet, rev. 0 freescale semiconductor 193 the hcs12 interface module accepts only aligned 16-bit wide read /write and 8-bit wide read transactions. the flexray cc module does not support 8-bit wide writ e accesses. the error indication bit illadr (illegal addr ess) is raised in the chier (see section 3.2.3.6.3, ?chi error register (chier) ?) in the event of an 8 bit write tr ansaction, or if an unaligned half word transaction is performed (detecte d if adr[0] is equal to 1 or if lstrb is equal to 1). data 0x0000 is presented to the host in this case. the rw_cc# signal indicates the directi on of data transfer for a transaction. int_cc# is an interrupt line that can be used for requesting, by means of the internal interrupt controller, a service routine from the hcs12 device. figure 3-145. flexray cc to hcs12 device connection with hcs12 ebi paged mode support pa d 0 pa d 1 5 eclk_cc rw_cc# to the phy mfr4200 ... xaddr14 xaddr19 ... lstrb int_cc# if_sel0/bgt/dbgt if_sel1/txd_bg1/txd_485 ... ... ... ... addr/data0 addr/data15 eclk r/w# ... xaddr14 xaddr19 ... lstrb irqn# to the phy vddio vddio hcs12 ... ... ... acs5 acs4 acs3 acs0 vddio vddio vddio ebi mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 194 freescale semiconductor figure 3-146. flexray cc to hcs12 device connection with hcs12 ebi unpaged mode support pa d 0 pa d 1 5 eclk_cc rw_cc# to the phy mfr4200 ... lstrb int_cc# if_sel0/bgt/dbgt if_sel1/txd_bg1/txd_485 ... ... addr/data0 addr/data15 eclk r/w# ... lstrb irqn# to the phy vddio vddio hcs12 ... ... ... xaddr[14:19] acs5 acs0 vddio vddio ebi 6 host controller interfaces mfr4200 data sheet, rev. 0 freescale semiconductor 195 figure 3-147. hcs12 interface address decoding and internal cs signal generation hcs12 interface of the cc 16 bit address /data demulti plexer pad[0..15] 16 bit 16 bit data[0..15] data signals adr[0..15] address signals 1 0 b i t 6 bit 6 bit address comparator1 acs[0..5] cs 16 bit adr[0..9] address signals adr[10..15] acs[0..5] xaddr[14..19] address comparator2 xaddr[14..19] 6 b i t ?000000? 2 bit adr[14..15] 2 b i t ?01? 2 bit 6 bit 6 bit address comparator3 ?1? 1 0 c & mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 196 freescale semiconductor 3.7.2.1 hcs12 interface signal and pin descriptions table 3-21. hcs12 interface signal and pin descriptions signal name hcs12 external bus flexray cc mcu interface pin function description name i/o name i/o 1 1 i ? input pin; o ? output pin; i/o ? input/output pin ad[0:15] addr/data[0:15] i/o* pad[0:15] i/o multiplexed external address data bus (ad0 is the lsb; ad15 is the msb) eclk# eclk# o eclk_cc# i internal bus clock output ? this output line is the clock system frequency of the hcs12 xaddr[14:19] xaddr[14:19] o xaddr[14:19] i hcs12 interface expanded address lines ? ( xaddr14 is the lsb of the hcs12 interface expanded address lines) acs[0:5] ? ? acs[0:5] i hcs12 interface, address select inputs . acs5: msb of the a ddress select inputs rd/wr# rd/wr# o rw_cc# i read/write ? indicates the direction of the data transfer for a transaction. a logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. lstrb# lstrb# o lstrb# i low-byte strobe ? indicates the type of bus access irq# irq# i int_cc# o interrupt request (level sensitive) ? one of the external lines that can request, by means of the internal interrupt controller, a service routine from the hcs12. if_sel[0:1] ? ? if_sel[0:1] i interface select ? flexray cc mcu interface configuration pins external 4/10 mhz output clock mfr4200 data sheet, rev. 0 freescale semiconductor 197 3.8 external 4/10 mhz output clock a continuous external 4/10 mhz output clock signal is provided by the cc on the clkout pin. this signal is always active after power-up of the cc in all cc states including the hard reset state. the clkout signal is disabled during the internal po wer-on and low voltage reset procedures (refer to chapter 5, ?clocks and reset generator ? for more information). the output frequency of the clkout signal is se lected by the clk_s0, clk_s1 input pins, in accordance with table 3-22 . note for information on clkout stabiliz ation timing parameters, refer to appendix a, ?electrical characteristics ?. 3.9 communication controller states 3.9.1 hard reset state protocol operation control: initiate hardware state. during this state, the cc initializes all internal regist ers to their specified hard reset default state (see section 3.2.2, ?register map summary ?). in the hard reset state: all the operation with prot ocol state machine are stopped. there is no transmission or reception on the flexray bus. there is no clock synchronization running. the cc host interface is stopped. the cc analyzes the input signals on the two pins if_sel0 and if_sel1 while leaving the hard reset state to configure the interface for the type of mcu (see section 3.7, ?host controller interfaces ?). the cc enters the hard reset state: according to the state of the hard reset pin (see section 5.2.2, ?reset generation and clkout control ?). table 3-22. clkout frequency selection pin clkout function clk_s0 clk_s1 0 0 4 mhz output 1 0 10 mhz output 0 1 40 mhz output 1 1 disabled (clkout output is ?0?) mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 198 freescale semiconductor note in the hard reset state, the host mcu type is not define d. if the host accesses the cc during this state, the cc ca n enter into an unpredictable state. therefore, the host is prohibited fr om performing any accesses to the cc when the cc is in the hard reset state. initialization of the cc is done on leav ing the hard reset state, i.e. on a rising edge of the hard reset signal (see section 3.2.3.1.3, ?magic number register (mnr) ?). after leaving the hard reset state, the host must wait until initialization is complete, before reading or writing to the controller. during this internal initialization procedure, the cc initializes its internal memory including following configuration/control parame ters of its message buffers. frame id = 0x0 ccfnr: cycle count mask and cy cle counter value fields = 0 bufcsnr: ? bufcmt = 0 ? cha, chb = 0 ?bt= 0 ? ccfe = 0 ? tt = 0 ? lock = 0 ?iflg = 0 ?valid = 0 ?iena = 0 ?cfg = 0 ?dataupd = 0 during the internal initialization pr ocedure the host must not access any of the cc registers except mnr (see section 3.2.3.1.3, ?magic number register (mnr) ), which acknowledges the end of the internal initialization procedure. the cc exits the hard reset state and enters the confi guration state, after the hard reset signal is negated (see section 3.2.3.2.1, ?module configuration register 0 (mcr0) ?). communication controller states mfr4200 data sheet, rev. 0 freescale semiconductor 199 3.9.2 configuration state protocol operation control: config state. during this state, the host configures the cc in accordance with the access scheme for cc internal resources (see section , ?receive, receive fi fo, and transmit message buff ers are accessible to the host mcu only through the active receive, active transmit, and active r eceive fifo buffers. ?) and the configuration principles (see section 3.5, ?message buffer handling and operations ?). in the configuration state: all operations with the protocol state machine are stopped. there is no transmission or reception on the flexray bus. there is no clock synchronization running. the host interface of the cc is operational. the host type is fixed af ter the hard reset state. all message buffers, afte r entering the configuration state from the hard reset state, are ?not used? buffers. the cc stores its configuration if it enters the configuration state from a state other than the hard reset state. if the host puts the cc into the configuration state by setting the config bit in mcr0 register to ?1? (see section 3.2.3.2.1, ?module configur ation register 0 (mcr0) ?), the cc configuration data will be held, except data that is initia lized when leaving the configuration state. on leaving the configuration state, some registers ar e cleared by the cc (this ope ration is highlighted in descriptions of those registers). the cc enters the configuration state: by leaving the hard reset state. according to the state of the conf ig bit in the mcr0 register (see section 3.2.3.2.1, ?module configuration register 0 (mcr0) ?). by leaving the sleep state or the diagnosis stop states. note the cc enters the configuration stat e immediately the mcr0 config bit is set. this may cause a pr otocol violation; the user must take care to ensure that entry to the configuration stat e does not cause a pr otocol violation. the cc exits from the configuration state a nd enters the normal state of operation (see section 3.9.4, ?normal active state ?). figure 3-148 represents a timing diag ram of the transition from the conf iguration state to the normal state. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 200 freescale semiconductor figure 3-148. timing diagram of cc state transi tion from configuration state to normal state 3.9.3 diagnosis stop state protocol operation control: freeze state. the diagnosis stop state is intended to support the u ser during host software off-line system diagnosis. it allows: the user to stop all protocol engine ope rations (frame transmission, reception, clock synchronization, etc.) except host interface operations, the host to read all host interface registers. in the diagnosis stop state: all operations of the protoc ol state machine are stopped. there is no transmission and no reception on the flexray bus. there is no clock synchronization running. the host interface is operational. all registers have the sam e access scheme as they ha ve in normal operation (see table 3-16 ); the cc enters the diagnosis stop state from the normal state of operation: if the host sets the diagstop bit in the mcr0 register (see section 3.2.3.2.1, ?module configuration register 0 (mcr0) ?). the host has written ?0? to the mcr0 bit in config, requesting the cc to leave the configuration state delay configured by the dcr in microticks cc starts entering the normal state cc is in the configuration state configuration state 100 1 microseconds programmed delay startup 4000 microticks delay note: 1 for a 40.000 mhz crystal connected to extal/xtal pins, or for 40.000 mhz cc_clk input clock. time communication controller states mfr4200 data sheet, rev. 0 freescale semiconductor 201 note the cc enters the diagnosis stop stat e immediately the diagstop bit is set. this may cause a protoc ol violation; the user mu st ensure that entry to the diagnosis stop state does not cause a protocol violation. the cc exits from the diagnosis stop state and enters the conf iguration state (see section 3.9.2, ?configuration state ?). 3.9.4 normal active state protocol operation control: normal active state. in the normal state, the cc s upports regular communication functi ons ? frame transmission, reception, clock synchronization, host interface operations, etc. in the normal state: the cc performs transmission and recepti on on the flexray bus, if configured. clock synchronization runs. the host interface is operational. all registers comply with the access scheme shown in table 3-16 . the cc enters the normal state from the configuration state: if the host clears the config bit in the mcr0 register to ?0? (see section 3.2.3.2.1, ?module configuration register 0 (mcr0) ?). the cc exits the normal state and enters: the configuration state, according to the st ate of the config bit in the mcr0 register the diagnosis stop state, according to the stat e of the diagstop bit in the mcr0 register. the debug state, according to the stat e of the dbg bit in the mcr0 register. the listen only state, according to the state of the lo bit in the mcr0 register. the listen only state, to deal wi th errors caused by clock synchroni zation failure (for more detailed information, refer to the pwd: clock synchronization chapter). the sleep state, according to the state of th e slprq and slpack bits in the mcr0 register. for the description of the slprq, slpack, config, diagstop, dbg and lo bits, see section 3.2.3.2.1, ?module configuration register 0 (mcr0) ?. note for a detailed description of the normal state, refer to the pwd: hw states and operation modes chapter. 3.9.5 normal passive state protocol operation control: normal passive state. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 202 freescale semiconductor in the normal passive state, the cc supports regular communication func tions (reception, clock synchronization, host interf ace operations, etc.), ex cept frame transmission. in the normal passive state: the cc receives frames on the flexray bus, if configured. the cc does not transmit an y frames on the flexray bus. clock synchronization runs. the host interface is operational. all registers comply with the access scheme shown in table 3-16 . the cc enters the normal passive stat e from the normal mode of operation: from the normal active state, if the clock synchronization failed (for more detailed information, refer to the pwd: cloc k synchronization chapter) note the cc enters the normal passive st ate at the end of the current communication cycle. the cc exits the normal passive state and enters: the configuration state, accor ding to the state of the config bit in the mcr0 register; the diagnosis stop state, according to the stat e of the diagstop bit in the mcr0 register; the debug state, according to the stat e of the dbg bit in the mcr0 register; the sleep state, according to the state of the slprq and slpack b its in the mcr0 register; (see section 3.2.3.2.1, ?module configuration register 0 (mcr0) ?). note for a detailed description of the listen state, refer to the pwd: hw states and operation modes chapter. 3.10 debug port 3.10.1 debug port overview the debug port is provided by means of two mfr4200 pins ? bgt/dbg2/if_sel0 and arm/dbg1/clk_s0. the debug port control register (see section 3.2.3.3.33, ?debug port control register (dbpcr) ?) selects the output functions for the se two pins. the functions are controlled independently of each other and, th erefore, the same or different output functions may be configured for the bgt/dbg2/if_sel0 and arm/dbg1/clk_s0 pins. note as the dbg1 and dbg2 signals are sh ared with the bus guardian output signals on the bgt/dbg2/if_sel0 a nd arm/dbg1/clk pins, the debug port pins are not accessible in appli cations where bus guardian devices are connected to the mfr4200. debug port mfr4200 data sheet, rev. 0 freescale semiconductor 203 3.10.2 debug port functions table 3-23 describes all debug port functions. table 3-23. debug port functions description function short name indicated by description protocol state change pcs rising edge of the si gnal the cc strobes every protocol state change (see section 3.2.3.4.1, ?protocol state register (psr) ?). slot start in static segment sss rising edge of t he signal the cc strobes every static slot start. minislot start mss rising edge of the signal the cc strobes every minislot start. rxd after glitch filter on channel a ragfa ? this function outputs data received on channel a rxd (rxd_bg1/rxd1_485 pin) after glitch filter processing. dynamic slot start on channel a dssa rising edge of t he signal the cc strobes every dynamic slot start on channel a. start of frame on channel a sfa rising edge of the signal the cc strobes every receive frame start on channel a. received syntactically correct an semantically valid frame indication on channel a rcfa rising edge of the signal the cc indicates every reception of a syntactically correct and semantically valid frame on channel a after 11 flexray bus bits, measured from the received frame end sequence. start of a communication cycle scc rising edge of the signal and its level the cc strobes every communication cycle start with a rising edge. this signal stays high during the communic ation cycle and the cc negates it (low) with the nit start. macrotick mts rising edge of the signal this f unction outputs the cc internal corrected macrotick. start of offset correction soc ris ing edge of the signal the cc strobes the time point during the nit when it performs the offset correction. rxd after glitch filter on channel b ragfb ? this function outputs data received on channel b rxd (rxd_bg2/rxd2_485 pin) after glitch filter processing. dynamic slot start on channel b dssb rising edge of t he signal the cc strobes every dynamic slot start on channel b. start of frame on channel b sfb rising edge of the signal the cc strobes every receive frame start on channel b. received syntactically correct an semantically valid frame indication on channel b rcfb rising edge of the signal the cc indicates every reception of a syntactically correct and semantically valid frame on channel b after 11 flexray bus bits measured from the received frame end sequence. mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 204 freescale semiconductor 3.10.3 debug port function timing figure 3-149 depicts a timing diagram for the start of comm unication cycle function an d the start of offset correction function, in relation to the communication cycle timing. figure 3-149. start of communication cycle an d start of offset correction functions timing the following debug functions indicate certain events with the rising edge and stay high for three clock cycles of the extal or cc_clk clock (see figure 3-150 ). protocol state change minislot start rxd after glitch filter on channel a dynamic slot start on channel a start of frame on channel a indication of syntactically co rrect and semantically valid frame received on channel a macrotick rxd after glitch filter on channel b dynamic slot start on channel b start of frame on channel b indication of syntactically co rrect and semantically valid frame received on channel b figure 3-150. timing for debug functions with three extal or cc_clk clock cycles of high state (logic ?1?) communication cycle start of communication cycle start of offset correction nit nit dynamic segement static segment symbol window static segment extal or cc_clk debug port signal debug port mfr4200 data sheet, rev. 0 freescale semiconductor 205 the slot start in static segment debug function indicates every slot start event in the static segment with a rising edge that stays high for one clock cycle of the extal or cc_clk clock (see figure 3-151 ): figure 3-151. slot start in static segment function timing extal or cc_clk debug port signal mfr4200 flexray communication controller mfr4200 data sheet, rev. 0 206 freescale semiconductor mfr4200 data sheet, rev. 0 freescale semiconductor 207 chapter 4 dual output voltage regulator (vreg3v3v2) 4.1 introduction the vreg3v3v2 is a dual output voltage regulator providing two separate 2.5 v (typical) supplies differing in the amount of current th at can be sourced. the regulator i nput voltage range is from 3.3 v up to 5 v (typical). 4.1.1 features the block vreg3v3v2 includes these distinctive features: ? two parallel, linear voltage regulators ? bandgap reference ? power-on reset (por) ? low-voltage reset (lvr) 4.1.2 modes of operation vreg3v3v2 can operate in two modes on mfr4200: ? full-performance mode (fpm) the regulator is active, providing the nominal supply voltage of 2.5 v with full current sourcing capability at both outputs. feat ures lvr (low-voltage reset) and por (power-on reset) are available. ? shutdown mode controlled by v regen (see device overview chap ter for connectivity of v regen ). this mode is characterized by minimum power consumption. the regulator outputs are in a high impedance state; only the por feature is available, and lvr is disabled. this mode must be used to di sable the chip intern al regulator vreg3v3v2, i.e., to bypass the vreg3v3v2 to use external supplies. 4.1.3 block diagram figure 4-1 shows the function principle of vreg3v3v2 by means of a block diagram. the regulator core reg consists of two parallel sub- blocks, reg1 and reg2, providing two independent output voltages. dual output voltage regulator (vreg3v3v2) mfr4200 data sheet, rev. 0 208 freescale semiconductor figure 4-1. vreg3v3 block diagram lv r por v ddr v dd por lvr ctrl v ss v ddosc v ssosc v regen reg reg2 reg1 pin v dda v ssa reg: regulator core ctrl: regulator control lvr: low voltage reset por: power-on reset v ssr dual output voltage regulator (vreg3v3v2) mfr4200 data sheet, rev. 0 freescale semiconductor 209 4.2 external signal description due to the nature of vreg3v3v2 being a voltage regulator providing the chip internal power supply voltages most signals are power s upply signals connected to pads. table 4-1 shows all signals of vreg3v 3v2 associated with pins. note check device overview chapter for connectivity of the signals. 4.2.1 v ddr , v ssr ? regulator power input signal v ddr is the power input of vreg3v3v2. all curren ts sourced into the regulator loads flow through this pin. a chip external decoupling ca pacitor (100 nf...220 nf, x7 r ceramic) between v ddr and v ssr can smoothen ripple on v ddr . for entering shutdown mode, pin v ddr must also be tied to ground on devices without a v regen pin. 4.2.2 v dda , v ssa ? regulator reference supply signals v dda /v ssa which are supposed to be relatively quiet are used to supply the analog parts of the regulator. internal precisi on reference circuits are supplied from th ese signals. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between v dda and v ssa can further improve the quality of this supply. table 4-1. vreg3v3v2 ? signal properties name port function reset state pull up v ddr ? vreg3v3v2 power input (positive supply) ? ? v ssr ? vreg3v3v2 power input (ground) ? ? v dda ? vreg3v3v2 quiet input (positive supply) ? ? v ssa ? vreg3v3v2 quiet input (ground) ? ? v dd ? vreg3v3v2 primary output (positive supply) ? ? v ss ? vreg3v3v2 primary output (ground) ? ? v ddosc ? vreg3v3v2 secondary output (positive supply) ? ? v ssosc ? vreg3v3v2 secondary output (ground) ? ? v regen (optional) ? vreg3v3v2 (optional) regulator enable ? ? dual output voltage regulator (vreg3v3v2) mfr4200 data sheet, rev. 0 210 freescale semiconductor 4.2.3 v dd , v ss ? regulator output1 (core logic) signals v dd /v ss are the primary outputs of vreg3v3v2 that provide the power supply for the core logic. these signals are connected to device pins to allow external decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode an external supply at v dd /v ss can replace the voltage regulator. 4.2.4 v ddosc , v ssosc ? regulator output2 (osc) signals v ddosc /v ssosc are the secondary outputs of vreg3v3v2 that provide the power supply for the oscillator. these signals are connect ed to device pins to allow extern al decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode an external supply at v ddosc /v ssosc can replace the voltage regulator. 4.2.5 v regen ? optional regulator enable this optional signal is used to shutdown vreg3v3v2. in that case v dd /v ss and v ddosc /v ssosc must be provided externally. shutdow n mode is entered with v regen being low. if v regen is high, the vreg3v3v2 is in reduced-power mode. for the connectivity of v regen see device overview chapter. note switching from fpm or rpm to sh utdown of vreg3v3v2 and vice versa is not supported while the cc is powered. 4.3 functional description block vreg3v3v2 is a voltage regulator as depicted in figure 4-1 . the regulator func tional elements are the regulator core (reg), a power -on reset module (por) and a low-vol tage reset module (lvr). there is also the regulator control block (ctrl) which manages the operating modes of vreg3v3v2. 4.3.1 reg ? regulator core vreg3v3v2, respectively its regulator core has two parallel, i ndependent regulation loops (reg1 and reg2) that differ only in the amount of current that can be sourced to the connected loads. therefore, only reg1 providing the supply at v dd /v ss is explained. the principle is also valid for reg2. the regulator is a linear series regulator with a bandgap reference in its fu ll-performance mode and a voltage clamp in reduced-power mode. a ll load currents flow from input v ddr to v ss or v ssosc , the reference circuits are connected to v dda and v ssa . 4.3.2 full-performance mode in full-performance mode, a fra ction of the output voltage (v dd ) and the bandgap reference voltage are fed to an operational amplifier. the amplified input voltage di fference controls the gate of an output driver. dual output voltage regulator (vreg3v3v2) mfr4200 data sheet, rev. 0 freescale semiconductor 211 4.3.3 por ? power on reset this functional block monitors output v dd . if v dd is below v pord , signal por is high; if it exceeds v pord , the signal goes low. the transition to low forces the cpu into the power-on sequence. due to its role during chip power -up, this module must be active in all operating modes of vreg3v3v2. 4.3.4 lvr ? low voltage reset block lvr monitors the primary output voltage v dd . if it drops below the assertion level (v lvra ) signal lvr asserts and when rising above the deassertion level (v lvrd ) signal lvr negates again. the lvr function is available only in full-performance mode. 4.3.5 ctrl ? regulator control this part contains digital functionality needed to control the operating modes. 4.4 resets this subsection describes how vreg3v3v2 controls the re set of the cc. the reset values of registers and signals are provided in section 3.2, ?memory map and registers? . possible reset sources are listed in table 4-2 . 4.4.1 power on reset during chip power-up the digital core ma y not work if its supply voltage v dd is below the por deassertion level (v pord ). therefore, signal por, which forces the other blocks of the device into reset, is kept high until v dd exceeds v pord . then por becomes low and the reset generator of the device continues the start-up sequence. 4.4.2 low voltage reset for information on low-voltage reset see section 4.3.4, ?lvr ? low voltage reset? . table 4-2. vreg3v3v2 ? reset sources reset source local enable power-on reset always active low-voltage reset always active dual output voltage regulator (vreg3v3v2) mfr4200 data sheet, rev. 0 212 freescale semiconductor mfr4200 data sheet, rev. 0 freescale semiconductor 213 chapter 5 clocks and reset generator 5.1 introduction this document describes the crg opera tion in functional mode and only those aspects of it useful to the end user. 5.1.1 features the main features of this block are: system clock generator depending on the mode : functional, scan or memory bist mode. system reset generation from the following possible events: ?power-on ?low voltage ? external pin reset reset control signal generation for th e flexray module?s clkout generator. clocks and reset generator mfr4200 data sheet, rev. 0 214 freescale semiconductor 5.2 functional description 5.2.1 mfr4200 pins relevant to the crg 5.2.2 reset generation and clkout control the crg will provide a system reset on any of the following events: power-on, low voltage, or low level detected at the reset# pin. entry into reset is as ynchronous and does not require a clock; however, the mfr4200 cannot sequence out of reset in f unctional mode without a system clock. the crg scans, during different peri ods depending on the origin of th e reset source, the interface and clkout selector pins: if_s el[0:1] and clk_s[0:1]. table 5-1. mfr4200 pins relevant to the crg pin n pin name in/out pin type 1 1 pc (pullup/down controlled) ? register controlled inte rnal weak pull up/down for a pin in the input mode. pd (pull down) ? internal weak pull down for a pin in the input mode. dc (drive strength controlled) ? register controlled drive strength for a pin in the output mode. z ? three-stated pin. od (open drain) ? output pin with open drain. reset state: ? all pins with the pc option have pullup/down resistors disabled. ? all pins with the dc option have full drive strength. functional description 1 test i - this pin must be tied to logic ?0?. 16 reset# i - hardware reset input 24 extal/cc_clk i - crystal driver / external clock pin 25 xtal i - crystal driver pin 32 bgt/dbg2/if_sel0 i/o dc/pd bus gua rdian tick / debug strobe point signal 2 / host interface selection 0 41 txd_bg1/txd1_485/ if_sel1 i/o dc/pd phy data transmitter output / rs485 data transmitter output / host interface selection 1 47 arm/dbg1/clk_s0 i/o dc/pd bus guardian arm signal / debug strobe point signal 1 / controller clock output select signal 0 48 mt/clk_s1 i/o dc/pd bus guardian macrotick / controller clock output select signal 1 52 eclk_cc i pc hcs12 clock input 63 clkout i/o dc clkout output, select able as disabled or 4/10/40 mhz. functional description mfr4200 data sheet, rev. 0 freescale semiconductor 215 note see section 3.7, ?host controller interfaces ? and section 3.8, ?external 4/10 mhz output clock ? for a description of the encoding of these pins. 5.2.2.1 power-on or low voltage reset when the power-on or low voltage reset signals are as serted, the crg sets the internal reset signal. the crg will negate synchronously the internal re set signal, approximately 16000 extal/cc_clk clock ticks after the negation of the powe r-on or low-voltage reset signals. while the internal reset si gnal is asserted due to a po wer-on or low-voltage situat ion, the pins clk_s[0:1] and if_sel[0:1] are latched and the clkout is disabled. after the crg nega tes the internal reset signal the flexray core will: 1. generate clkout signal with frequency indi cated by the values latched in clk_s[0:1], 2. select the required host interface with the last value latched in if_sel[0:1] signals. figure 5-1. power-on reset figure 5-2. low voltage reset vdd power_on reset internal_reset ~16000 latching window clk_s x - if_sel x clkout vdd power_on reset internal_reset clk_sx ? if_selx clkout ~16000 latching window low_level_voltage low_voltage internal_reset ~ 16000 clk_s x - if_sel x clkout latching low_voltage internal_reset clk_sx ? if_selx clkout latching window ~16000 clocks and reset generator mfr4200 data sheet, rev. 0 216 freescale semiconductor 5.2.2.2 external reset when the reset# pin is asserted the crg sets the internal reset signal. the crg wi ll negate the internal reset signal approximately 16 extal/cc_clk clock ticks afte r the de-assertion of reset#. while the internal reset signal is a sserted due to an external reset, the pins clk_s[0:1] and if_sel[0:1] are latched but the clkout signal is still be generated. figure 5-3 shows an external reset sequence. figure 5-3. external reset ~ 16 internal_reset reset latching clkout clk_s x - if_sel x reset# reset# internal_reset clk_sx ? if_selx clkout latching window ~16 mfr4200 data sheet, rev. 0 freescale semiconductor 217 chapter 6 oscillator (oscv2) 6.1 introduction the oscv2 module provides one oscillator concept: a robust full swing pierce oscillator with the possibility to feed in an external square wave 6.1.1 features the pierce osc option provid es the following features: wider high frequency operation range no dc voltage applied across the crystal full rail-to-rail (2.5 v nominal) swing oscillation with low em susceptibility fast startup common features: operation from the v ddosc 2.5 v (nominal) supply rail 6.1.2 modes of operation one mode of operation exists: full swing pierce oscillator mode, which can also be used to feed in an externally generated square wave suitable for high frequenc y operation and harsh environments 6.2 external signal description this section lists and describes th e signals that connect off chip. 6.2.1 v ddosc and v ssosc ? osc operating voltage, osc ground these pins provide the operating voltage (v ddosc ) and ground (v ssosc ) for the oscv2 circuitry. this allows the supply voltage to the oscv2 to be independently bypassed. 6.2.2 extal and xtal ? clock/crystal source pins these pins provide the interface for either a crystal or a cmos compatible clock to control the internal clock generator circuitry. extal is the external clock input or the input to the crystal oscill ator amplifier. xtal is the output of the crystal o scillator amplifier. all the cc intern al system clocks are derived from oscillator (oscv2) mfr4200 data sheet, rev. 0 218 freescale semiconductor the extal input frequency. in full stop mode (pstp = 0) the extal pin is pulled down by an internal resistor of typical 200 k ? . note freescale semiconductor re commends an evaluati on of the application board and chosen resonato r or crystal by the res onator or crystal supplier . the crystal circuit is changed from standard. the pierce circuit is not suited for overtone resonators and crystals without a careful component selection. for more information on extal and xtal, see section 2.2.3.22, ?xtal ? crystal driver pin ?. 6.3 functional description the oscv2 block has two external pins, extal and xtal. the oscillat or input pin, extal, is intended to be connected to either a crystal or an external clock source. a buffered extal signal, oscclk, becomes the inte rnal reference clock. to improve noise immunity, the oscillator is powered by the v ddosc and v ssosc power supply pins. mfr4200 data sheet, rev. 0 freescale semiconductor 219 appendix a electrical characteristics a.1 general note the electrical characteristics given in this appendix are preliminary and must be used as a guide only. values cannot be gua ranteed by freescale and are subject to change without notice. note the part is specified and tested over the 5 v and 3.3 v ranges. for the intermediate range, generally the el ectrical specifications for the 3.3 v range apply, but the part is not tested in production test in the intermediate range. this appendix provides the most accurate electrical inform ation for the mfr4200 device available at the time of publication. this introduction is intended to give an overview on several common topics lik e power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplemen t are guaranteed by various methods. the following classifications are used and the pa rameters are tagged accordingly in the column labeled ?c? in the parameter tables, where appropriate. p: parameters that are guaranteed during production testing on each individual device. c: parameters that are achieved by the design char acterization by measuring a statistically relevant sample size across process variations. t: parameters that are achieved by design char acterization on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d: parameters that are derived mainly from simulations. electrical characteristics mfr4200 data sheet, rev. 0 220 freescale semiconductor a.1.2 power supply the mfr4200 uses several pins to supply power to the i/o pins, oscillator and the digital core. the vdda, vssa pair supplies the internal voltage regulator. the vddx, vssx, vddr and vssr pairs supply the i/ o pins, vddr supplies also the internal voltage regulator. vdd2_5 and vss2_5 are the supply pins for the digital logic, vddosc , vssosc supply the oscillator. vdda, vddx, vddr as well as v ssa, vssx, vssr are connected by anti-parallel diodes for esd protection. note in the following context, vdd5 is used for either vdda, vddr and vddx; vss5 is used for either vs sa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the curren ts flowing into the vdda, vddx and vddr pins. vdd is used for vdd2_5 and vddos c, vss is used for vss2_5 and vssosc. idd is used for the current flowing into vdd2_5. a.1.3 pins there are four groups of functional pins. a.1.3.1 3.3v i/o pins those i/o pins have a nominal level of 3.3v. this cla ss of pins is comprised of all i/o pins (all mfr4200 pins excluding extal, xtal and all power supply pins ).the internal structure of all those pins is identical, however some of the functio nality may be disabled. e.g. for th e input-only pins the output drivers are disabled permanently. a.1.3.2 oscillator the pins extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddosc. a.1.3.3 vddr this pin is used to enable the on chip voltage regulator. general mfr4200 data sheet, rev. 0 freescale semiconductor 221 a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could re sult in external power supply going out of regulation. ensure external v dd5 load will shunt current greater than maxi mum injection current. this will be the greatest risk when the cc is not consum ing power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). table a-1. absolute maximum ratings 1 1 beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 -0.3 6.5 v 2 digital logic supply voltage 2 2 the device contains an internal voltage regulator to ge nerate the logic and osc supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd -0.3 3.0 v 3 oscillator supply voltage 2 v ddosc -0.3 3.0 v 4 voltage difference vddx to vddr and vdda ? vddx -0.3 0.3 v 5 voltage difference vssx to vssr and vssa ? vssx -0.3 0.3 v 6 digital i/o input voltage v in -0.3 6.5 v 7 extal, xtal inputs v ilv -0.3 3.0 v 8 instantaneous maximum current single pin limit for all digital i/o pins 3 3 all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . i d -25 +25 ma 9 instantaneous maximum current single pin limit for extal, xtal 4 4 those pins are internally clamped to v ssosc and v ddosc . i dl -25 +25 ma 10 operating temperature range (packaged) t a -40 +125 o c 11 operating temperature range (junction) t j -40 +150 o c 12 storage temperature range t stg ? 65 155 c electrical characteristics mfr4200 data sheet, rev. 0 222 freescale semiconductor a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for automotive grade integrated circuits. during the de vice qualification esd stresses we re performed for the human body model (hbm), the machine model (mm) and the charge device model. a device will be defined as a failure if after exposure to esd pul ses the device no longe r meets the device specification. complete dc parametric and functional testing is perf ormed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. table a-2. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative -- 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative -- 3 3 latch-up minimum input voltage limit - -2.5 v maximum input voltage limit - 7.5 v table a-3. esd and latch-up protection characteristics num c rating symbol min max unit 1 t human body model (hbm) v hbm 2000 - v 2 t machine model (mm) v mm 200 - v 3 t charge device model (cdm) v cdm 500 - v 4 t latch-up current at t a = 125 c positive negative i lat +100 -100 - ma 5 t latch-up current at t a = 27 c positive negative i lat +200 -200 -ma general mfr4200 data sheet, rev. 0 freescale semiconductor 223 a.1.7 operating conditions this chapter describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calculations refer to section a.1.8, ?power dissipation and thermal characteristics ?. a.1.8 power dissipation an d thermal characteristics power dissipation and therma l characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: eqn. a-1 t j = junction temperature [c] t a = ambient temperature [c] p d = total chip power dissipation [w] ja = package thermal resistance [c/w] the total power dissipation can be calculated from: table a-4. operating conditions rating symbol min typ max unit oscillator and quartz frequency f osc - 40.000 40.000 mhz quartz overtone fundamental frequency quartz frequency stability at t j f stb -1500 300 1500 ppm voltage difference vddx to vddr and vdda d vddx -0.1 0 0.1 v voltage difference vssx to vssr and vssa d vssx -0.1 0 0.1 v i/o, regulator and analog supply v dd5 2.97 3.3 5.5 v digital logic supply voltage 1 1 the device contains an internal voltage regulator to generate the logic and osc supply out of the i/o supply. v dd 2.25 2.5 2.75 v oscillator supply voltage 1 v ddosc 2.25 2.5 2.75 v operating junction temperature range t j -40 - 140 o c operating ambient temperature range 2 2 refer to section a.1.8, ?power dissipation and thermal characteristics ? for more information about the relation between ambient temperature t a and device junction temperature t j . t j -40 27 125 o c t j t a p d ja ? () + = electrical characteristics mfr4200 data sheet, rev. 0 224 freescale semiconductor eqn. a-2 pint = chip internal power dissipation [w] two cases with internal voltage regulator en abled and disabled mu st be considered: 1. internal voltage regulator disabled eqn. a-3 eqn. a-4 p io is the sum of all output currents on i/o ports associated with vddx and vddr. for r dson is valid: eqn. a-5 respectively eqn. a-6 2. internal voltage regulator enabled eqn. a-7 i ddr is the current shown in table a-8 and not the overall current flowing into vddr, which additionally contains the current flowing in to the external loads with output high. eqn. a-8 p io is the sum of all output currents on i/o ports associated with vddx and vddr. p d p int p io + = p int i dd v dd ? i ddosc v dd osc ? i dda +v dda ? + = p io r dson i i io i 2 ? = r dson v ol i ol ------------ f o r o u t p u t s d r i v e n l o w ; = r dson v dd5 v oh ? i oh --------------- --------------------- for outputs driven high ; = p int i ddr v ddr ? i dda v dda ? + = p io r dson i i io i 2 ? = general mfr4200 data sheet, rev. 0 freescale semiconductor 225 table a-5. thermal package simulation details num rating symbol value unit 1 junction to ambient lqfp64, single sided pcb 1,2 , natural convection 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissi pation of other components on the board, and board thermal resistance. 2 per semi g38-87 and eia/jedec standard 51-2 with the single layer horizontal pc board according to eia/jedec standard 51-3 r ja 67 o c/w 2 junction to ambient lqfp64, double sided pcb with 2 internal planes 1,3 , natural convection 3 per eia/jedec standard 51-6 with the four layer horizontal pc board (double-sided pcb with two internal planes) according to eia/jedec standard 51-7 r jma 52 o c/w 3 junction to ambient lqfp64 (@200 ft/min), single sided pcb 1,3 r jma 60 o c/w 4 junction to ambient lqfp64 (@200 ft/min), double sided pcb with 2 internal planes 1,3 r jma 48 o c/w 5 junction to board lqfp64 4 4 thermal resistance between the die and the printed circuit board per eia/jedec standard 51-8. board temperature is measured on the top surface of the board near the package. r jb 34 o c/w 6 junction to case lqfp64 5 5 thermal resistance between the die and t he case top surface as measured by the cold plate method (mil spec-883 method 1012.1). r jc 17 o c/w 7 junction to package top lqfp64 6 , natural convection 6 thermal characterization parameter indicating the temperatur e difference between package top and the junction temperature per eia/jedec standard 51-2. jt 3 o c/w electrical characteristics mfr4200 data sheet, rev. 0 226 freescale semiconductor a.1.9 i/o characteristics this section describes the characteris tics of all 3.3v i/o pins. all parame ters are not always applicable, e.g. not all pins feature pullup/pulldown resistances. table a-6. 5v i/o characteristics (v dd5 = 5v) conditions are shown in figure a-4 , unless otherwise noted. num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 --v t input high voltage v ih --v dd5 +0.3 v 2 p input low voltage v il - - 0.35*v dd5 v t input low voltage v il v ss5 -0.3 - - v 3 c input hysteresis v hys -250-mv 4 p high impedance (off-state) leakage current v in =v dd or v ss , all input/output and output pins i in -2.5 - +2.5 ua 5 p output high voltage (pins in output mode) @50% partial drive i oh = -2ma v oh v dd5 -0.8 - - v 6 p output high voltage (pins in output mode) @100% full drive i oh = -10ma v oh v dd5 -0.8 - - v 7 p output low voltage (pins in output mode) @50% partial drive i ol = +2ma v ol --0.8v 8 p output low voltage (pins in output mode) @100% full drive i ol = +10ma v ol --0.8v 9 p internal pullup device current, tested at v il max i pul - - -130 ua 10 p internal pullup device current, tested at v ih min. i puh -10 - - ua 11 p internal pulldown device current, tested at v ih min. i pdh --130ua 12 p internal pulldown device current, tested at v il max i pdl 10 - - ua 13 d input capacitance (input, input/output pins) c in -7-pf 14 t injection current 1 1 refer to section a.1.4, ?current injection ?, for more information. ma single pin limit i ics -2.5 - 2.5 total device limit. sum of all injected currents i icp -25 - 25 15 p load capacitance 50% partial drive 100% full drive c l -- 25 50 pf general mfr4200 data sheet, rev. 0 freescale semiconductor 227 table a-7. 3.3v i/o characteristics (v dd5 = 3.3v) conditions are v ddx =3.3v +/-10% temperature from -40 o c to +140 o c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 --v t input high voltage v ih --v dd5 +0.3 v 2 p input low voltage v il - - 0.35*v dd5 v t input low voltage v il v ss5 -0.3 - - v 3 c input hysteresis v hys - 250 - mv 4 p high impedance (off-sta te) leakage current v in =v dd or v ss , all input/output and output pins i in -2.5 - +2.5 ua 5 p output high voltage (pins in output mode) @50% partial drive i oh = -0.75ma v oh v dd5 -0.4 - - v 6 p output high voltage (pins in output mode) @100% full drive i oh = -4.5ma v oh v dd5 -0.4 - - v 7 p output low voltage (pins in output mode) @50% partial drive i ol = +0.9ma v ol --0.4v 8 p output low voltage (pins in output mode) @100% full drive i ol = +5.5ma v ol --0.4v 9 p internal pullup device current, tested at v il max i pul ---60ua 10 p internal pullup device current, tested at v ih min. i puh -6 - - ua 11 p internal pulldown device current, tested at v ih min. i pdh - - 60 ua 12 p internal pulldown device current, tested at v il max i pdl 6--ua 13 d input capacitance (input, input/output pins) c in -7-pf 14 t injection current 1 1 refer to section a.1.4, ?current injection ? for more information. ma single pin limit i ics -2.5 - 2.5 total device limit. sum of all injected currents i icp -25 - 25 15 p load capacitance 50% partial drive 100% full drive c l -- 25 50 pf electrical characteristics mfr4200 data sheet, rev. 0 228 freescale semiconductor a.1.10 supply currents this section describes the current c onsumption characteristics of the devi ce as well as the conditions for the measurements. a.1.10.1 measurement conditions all measurements are without output load s. unless otherwise not ed the currents are me asured with internal voltage regulator enabled and a 40 mhz oscillator in standard pierce mode. production testing is performed using a square wave signal at the extal input. table a-8. supply current characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 p run supply currents internal regulator enabled -40 ci dd5 --49.901ma 25 c--50.563 70 c--tbd 85 c--tbd 100 c--tbd 105 c--tbd 120 c--tbd 125 c--tbd 140 c--51.047 voltage regulator (vreg) mfr4200 data sheet, rev. 0 freescale semiconductor 229 a.2 voltage regulator (vreg) a.2.1 operating conditions table a-9. voltage regulator - operating conditions conditions are shown in ta b l e a - 4 unless otherwise noted num c characteristic symbol min typical max unit 1 p input voltages v vddr,a 2.97 ? 5.5 v 2 p regulator current shutdown mode i reg ?tbd40 a 3 p output voltage core full performance mode shutdown mode v dd 2.45 ? 2.5 ? 1 1 high impedance output 2.75 ? v v 4 p output voltage osc full performance mode shutdown mode v ddosc 2.35 ? 2.5 ? 2 2 high impedance output 2.75 ? v v 5 p low voltage reset 3 assert level 3 monitors v dd , always active v lv r a 2.25 ? ? v 6 c power-on reset 4 assert level deassert level 4 monitors v dd , always active v pora v pord 0.97 ? ? ? ? 2.05 v v electrical characteristics mfr4200 data sheet, rev. 0 230 freescale semiconductor a.2.2 chip power-up and voltage drops voltage regulator sub modules por (power-on reset) and lvr (low voltage reset) handle chip power-up or drops of the supply voltage. their function is described in figure a-1 . figure a-1. voltage regulator ? chip power-up and voltage drops (not scaled) a.2.3 output loads a.2.3.1 resistive loads on-chip voltage regulator intended to supply the intern al logic and oscillator ci rcuits allows no external dc loads. a.2.3.2 capacitive loads the capacitive loads are specified in figure a-10 . ceramic capacitors with x7 r dielectricum are required table a-10. voltage regulator recommended capacitive loads num characteristic symbol min typical max unit 1 vdd external capacitive load c ddext 200 440 12000 nf 3 vddosc external capacitive load c ddoscext 90 220 5000 nf v lvrd v lvra v pord por lvr t v v dd reset and oscillator mfr4200 data sheet, rev. 0 freescale semiconductor 231 a.3 reset and oscillator this section summarizes th e electrical characteristics of the various startup sc enarios for the oscillator. a.3.1 startup table a-11 summarizes several startup char acteristics explained in this section. detail ed description of the startup behavior can be found in the mfr4200 cl ock and reset generator (crg) block user guide. a.3.1.1 por the release level v porr (see table a-9 ) and the assert level v pora (see table a-9 ) are derived from the v dd supply. they are also valid if the device is po wered externally. after re leasing the por reset the oscillator is started. the fastest st artup time possible is given by n uposc . there is no clock monitoring function implemented. a.3.1.2 lvr the assert level v lvr a (see table a-9 ) is derived from the v dd supply. the fastest startup time possible is given by n uposc . there is no clock monitoring function implemented. a.3.1.3 external reset when external reset is asserte d for a time greater than pw rstl the crg module generates an internal reset, and the cc starts ope rations without doing a clock quality chec k, if there was an oscillation before reset. table a-11. startup characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 t por release level v porr - - 2.07 v 2 t por assert level v pora 0.97 - - v 3 d reset input pulse width, minimum input time pw rstl 2- -t osc 4 d startup from external reset negation n psst 25 27 30 n osc electrical characteristics mfr4200 data sheet, rev. 0 232 freescale semiconductor a.3.2 oscillator the device features an internal pierce oscillat or. the device does not have a clock monitor. a.4 ami interface timing diagram the cc ami interface read/write timing diagram is shown on the figure a-2 . writing to the device is accomplished when chip enable(ce#) and write enable (we#) inputs are low (asserted). reading from the device is accomplished when chip enable (ce#) and output enable (oe#) are low (asserted) while the write enable (we#) is high (negated). the input/output pins (d[15:0]) ar e in a high-impedance state when th e device is not selected (ce# is high), the outputs are disabled (oe# is high) or during a write operation (ce# is low, we# is low). table a-12. oscillator characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 c crystal oscillator range (pierce) 1 1 depending on the crystal a damping series resistor might be necessary f osc 0.5 - 40 mhz 2 p startup current i osc 100 - - a 3 c oscillator start-up time t uposc --tbdms 6 p external square wave input frequency f ext 0.5 - 50 mhz 7 d external square wave pulse width low t extl 9.5 - - ns 8 d external square wave pulse width high t exth 9.5 - - ns 9 d external square wave rise time t extr --1ns 10 d external square wave fall time t extf --1ns 11 d input capacitance (extal, xtal pins) c in -7-pf 12 c dc operating bias in pierce mode on extal pin v dcbias -tbd-v ami interface timing diagram mfr4200 data sheet, rev. 0 freescale semiconductor 233 figure a-2. ami interface read and write timing diagrams ce# a[9..1] we# d[15..0] ?1? data valid address valid high-z high-z read cycle t rc t ace ce# a[9..1] we# d[15..0] data valid address valid high-z high-z write cycle t wc t sce t sd t hd t cewe t pwe oe# t doe t lzoe t hzoe t sar t har t oeh t hoe oe# ?1? t weh t loe t saw t haw electrical characteristics mfr4200 data sheet, rev. 0 234 freescale semiconductor figure a-3. ami interface write-after-read transactions timing diagram figure a-4. ami interface read-after-write transactions timing diagram ce# a[9..1] we# d[15..0] ?1? data valid address valid high-z read cycle data valid address valid high- z write cycle t oewe oe# ?1? high-z ?1? data valid address valid high-z high- z read cycle ce# a[9..1] we# d[15..0] data valid address valid high- z write cycle t weoe oe# ?1? ami interface timing diagram mfr4200 data sheet, rev. 0 freescale semiconductor 235 table a-13. ami interface ac switching characteristics over the operating range characteristic symbol min max unit read cycle read time cycle t rc 155 - ns address setup read t sar 5-ns address hold read t har 50 - ns oe# low to data valid t doe - 145 ns oe# high time t hoe 30 - ns oe# low time t loe 150 - ns oe# low to low-z t lzoe 20 - ns oe# high to high-z t hzoe -15ns oe# high to ce# high t oeh 0-ns we# high to oe# low t weoe 80 - ns write cycle write time cycle t wc 50 - ns address setup write t saw 30 - ns address hold write t haw 5-ns ce# low to write end t sce 50 - ns data set-up to write end t sd 30 - ns data hold from write end t hd 5-ns we# pulse width t pwe 30 - ns we# high time t weh 55 - ns write end to ce# high t cewe 30 - ns oe# high to we# low t oewe 15 - ns electrical characteristics mfr4200 data sheet, rev. 0 236 freescale semiconductor a.5 hcs12 interface timing diagram the hcs12 device external bus is synchronous with clock frequency up to 8 mhz. signals are sampled on the both eclk# edges (see figure a-5 ). the hcs12 host addresses the cc as a sl ow memory device. due to that the hcs12 eclk external clock signal must be stretched. in the mfr4200 the output ec lk clock must be stretched by 3 periods of the hcs12 internal bus-rate clock. the cc hcs12 interface read/write timing diagram is shown in figure a-5 . for more information regarding th e hcs12 and hcs12 programming, refer to the hcs12 v1.5 core user guide, available at http://www.freescale.com/f iles/microcontrollers/doc/r ef_manual/s12cpu15ug.pdf. figure a-5. hcs12 interface read/write timing diagram acs eclk (x)addr/data (write) r/w (x)addr/data (read) lstrb data data data data (x)addr (x)addr 1 2 3 4 5 6 7 8 9 10 11 13 12 14 15 20 2 1 22 acs hcs12 interface timing diagram mfr4200 data sheet, rev. 0 freescale semiconductor 237 table a-14. hcs12 interface timing parameters num rating min max units restric- tion 1 1 column restriction: - cc limitation by the communication controller but complies to hcs12. - hcs12 limitation because of hcs12 specification. 1 pulse width, eclk low 1/cc_clk {25} 2 3 2 { .. } - values in ns if the cc_clk = 40 mhz . 3 if the parameter is not met then eclk signal deassertion c annot be sampled and the write/ read window cannot be calculated. --nscc 2 pulse width, eclk high 4/cc_clk {100}+[14] - - ns cc 3,11 address valid time to e rise 4 4 (x)addr and lstrb are taken over by the c ontroller with the rising edge of the eclk. -11--nshcs12 4 write data delay time - - - 7 ns hcs12 5 eclk rise to write data invalid 3/cc_clk {75}-[4] - - ns cc 6(4) write data hold time - 2 - - ns hcs12 7 rw delay time - - - 7 ns hcs12 8 rw valid time to eclk rise - 14 - - ns hcs12 9 rw hold time - 2 - - ns hcs12 10 data hold to address - 2 - - ns hcs12 12 multiplexed address hold time - 2 - - ns hcs12 13 eclk high access time (eclk high to read data valid) 2/cc_clk {50} 3/cc_clk {75} ns cc 14 read data setup time - 13 - - ns hcs12 15 read data hold time - 0 - - ns hcs12 20 low strobe delay time - - - 7 ns hcs12 21 low strobe valid to eclk rise - 14 - - ns hcs12 22 low strobe hold time - 2 - - ns hcs12 electrical characteristics mfr4200 data sheet, rev. 0 238 freescale semiconductor 64-pin lqfp package mfr4200 data sheet, rev. 0 freescale semiconductor 239 appendix b package information b.1 64-pin lqfp package figure b-1. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 1) package information mfr4200 data sheet, rev. 0 240 freescale semiconductor figure b-2. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 2) 64-pin lqfp package mfr4200 data sheet, rev. 0 freescale semiconductor 241 figure b-3. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 3) package information mfr4200 data sheet, rev. 0 242 freescale semiconductor 64-pin lqfp package mfr4200 data sheet, rev. 0 freescale semiconductor 243 appendix c printed circuit board layout recommendations the pcb must be laid out carefully to ensure prope r operation of the voltage regulator and the cc. the following rules must be observed: every supply pair must be decoupled by a cerami c capacitor connected as near as possible to the corresponding pins (cd). the central point of the ground star should be the vssr pin. low-ohmic low-inductance connections should be used between vssx and vssr. vssosc must be directly connected to vssr. traces of vssosc, extal and xtal must be kept as short as possible. occupied board area for c1, c2, c3 and q should be as small as possible. other signals or supply lines should not be rout ed under the area occupied by c1, c2, c3, and q and the connection area of the cc. the central power input should be fed in at the vdda/vssa pins. figure c-1 shows a recommended pcb layout (64-pin lqfp) for standard pi erce oscillator mode, while table c-1 provides suggested values for the external components. table c-1. suggested external component values component purpose type value c1 osc load cap ceramic x7r 2pf c2 osc load cap ceramic x7r 2pf c3 vddosc filter cap ceramic x7r 100? 220nf c4 vdda filter cap ceramic x7r 100? 220nf cd vddr, vddx filter cap cer amic x7r/tantalum 100? 220nf cload vdd2_5 filter cap ceramic x7r 100? 220nf r b osc res 1 mohm r s osc res 0 ohm (i.e. short-circuit_ q quartz ndk nx8045ga 40 mhz printed circuit board layout recommendations mfr4200 data sheet, rev. 0 244 freescale semiconductor figure c-1. recommended pcb layout (64-pin lqfp) for standard pierce oscillator mode mfr4200 data sheet, rev. 0 freescale semiconductor 245 appendix c mfr4200 protocol implementation document c.1 introduction c.1.1 purpose this document is an appendix to the mfr4200 flex ray microcontroller data sheet (mfr4200v2). it describes the flexray protocol implementation in the mfr4200. c.1.2 structure this appendix follows the structure of the flexra y communications system protocol specification v1.1 (ps v1.1). each section e xplains whether the implem entation in the mfr4200 is identical to the ps v1.1 or is realized with an intermediate solution. where only the section headline is provided, the implementation is compliant with the ps v1.1. c.1.3 references 1. flexray communications system protocol specification v1.1 (int ermediate consortium baseline) (ps v1.1/pwd) 2. mfr4200 flexray microcontro ller data sheet (mfr4200v2) mfr4200 protocol implementation document mfr4200 data sheet, rev. 0 246 freescale semiconductor c.2 overall protocol state machine the mfr4200 implements the overall protocol st ate machine according to ps v1.1/pwd, with differences presented below. figure c-1. protocol operation control (poc) - 1 host: wakeup startup protocol operation control (poc) wakeup reset status information initiate hardware config host: config complete take over config data vclockcorrection- failedcounter:=0 normal_active psyncslot ? else = 0 codec on a (normal), codec on b (normal), fsp control on a (go), fsp control on b (go), mas control on a (all), mas control on b (all), csp control (nosync) codec on a (normal), codec on b (normal), fsp control on a (go), fsp control on b (go), mas control on a (all), mas control on b (all), csp control (sync) codec on a (init), codec on b (init), fsp control on a (init), fsp control on b (init), mas control on a (init), mas control on b (init), csp control (init) overall protocol state machine mfr4200 data sheet, rev. 0 freescale semiconductor 247 figure c-2. protocol operation control (poc) - 2 * low voltage hardware reset activated freeze internal error host: config config transmitter off * (freeze) host: freeze red state transmitter off cycle start (zcyclecounter) normal_active, normal_passive - host: config * config transmitter off not implemented for fpga v8.x mfr4200 protocol implementation document mfr4200 data sheet, rev. 0 248 freescale semiconductor figure c-3. poc ? normal operation vclockcorrectionfailed:=0 normal_active vclockcorrectionfailed := vclockcorrectionfailed + 1 vclockcorrection- failed ? missing_rate successful limit_reached pallowfreeze- duetoclock ? false >= gmaxwithoutclockcorrection- fatal true >= gmaxwithoutclockcorrection- passive vclockcorrection- failed ? else zclockstate ? zcyclecounter ? odd even clocksyncstate(zclockstate, zstartuppairs, zrefpair) else ready normal_passive codec on a (init), codec on b (init), fsp control on a (init), fsp control on b (init), mas control on a (init), mas control on b (init), csp control (init) codec on a (normal), codec on b (normal), fsp control on a (go), fsp control on b (go), mas control on a (noce), mas control on b (noce), csp control (nosync) coding and decoding mfr4200 data sheet, rev. 0 freescale semiconductor 249 figure c-4. poc ? passive operation c.3 coding and decoding the implementation is compliant with ps v1.1, with the exception that th e wakeup symbol is not detected. c.3.1 overview the implementation is compliant with ps v1.1. c.3.2 nrz coding the implementation is compliant with ps v1.1. normal_passive true clocksyncstate(zclockstate, startuppairs, zrefpair) vclockcorrection- failed ? < gmaxwithoutclock- correctionfatal vclockcorrectionfailed := vclockcorrectionfailed + 1; < gmaxwithoutclock- correctionfatal pallowfreeze- duetoclock ? true else false zstartupnodes? false false pallowpassive- tofreeze ? true vclockcorrection- failed ? else vclockcorrectionfailed := 0 limit_reached missing_rate successful zclockstate ? zcyclecounter ? odd even freeze normal_active psyncslot ? else = 0 codec on a (init), codec on b (init), fsp control on a (init), fsp control on b (init), mas control on a (init), mas control on b (init), csp control (init) codec on a (normal), codec on b (normal), fsp control on a (go), fsp control on b (go), mas control on a (all), mas control on b (all), csp control (sync) codec on a (normal), codec on b (normal), fsp control on a (go), fsp control on b (go), mas control on a (all), mas control on b (all), csp control (nosync) =1 >1 pstartupnode? mfr4200 protocol implementation document mfr4200 data sheet, rev. 0 250 freescale semiconductor c.3.3 nrz decoding the implementation is compliant with ps v1.1. c.3.3.1 nfz decoding principles the implementation is compliant with ps v1.1. c.3.3.2 frame decoding the implementation is compliant with ps v1.1. c.3.3.3 symbol decoding the implementation is compliant with ps v1.1. c.3.3.3.1 collision resolution symbol the implementation is compliant with ps v1.1. c.3.3.3.2 wakeup symbol mfr4200 can generate a wakeup symbol in accordance with section c.3.2, ?nrz coding ?. however, the implementation does not recogni ze a wakeup symbol. see also section c.7.2, ?cluster wakeup ?. c.3.3.4 decoding error the implementation is compliant with ps v1.1. c.3.4 signal integrity the implementation is compliant with ps v1.1. c.4 frame format the implementation is compliant with ps v1.1. note the semantic of the null fram e bit has been inverted compared with previous implementations, to be compliant with ps v1.1. c.5 media access control the implementation is compliant with ps v1.1. note due to the implementation, there is a lower boundary gdnit (see section 3.2.3.3.18, ?network idle time configuration register (nitcr) . frame and symbol processing mfr4200 data sheet, rev. 0 freescale semiconductor 251 c.6 frame and symbol processing the implementation is compliant with ps v1.1, with the following exceptions. stup is not indicated to the host. data received during startup is not provided to the host. c.7 wakeup, startup, and reintegration c.7.1 introduction the implementation is compliant with ps v1.1. c.7.2 cluster wakeup the functionality of the wakeup is implemented in part only. the con troller can generate wakeup symbols on configurable channels and rep eat them for a configurable number of times in accordance with wakeup send. wakeup listen is not implemented. after comple ting wakeup send, the controller returns to the config state. c.7.3 communication startup and reintegration clearing the coldstart inhibit bit after leaving 'pc_reset' is not su pported in mfr4200. this applies for the following subsections. c.7.3.1 definitions and properties the implementation is compliant with ps v1.1. c.7.3.2 principle of operation the implementation is compliant with ps v1.1. c.7.3.3 coldstart inhibit mode the implementation is compliant with ps v1.1. c.7.3.4 startup state diagram the implementation is compliant with ps v1.1. however, the protocol state indi cated in the host interface is incorrect for a short time, in the following case: when the node has unsuccessfully perf ormed a coldstart, and the number of remaining coldstart attempts is 0, the host interface indicates that the controller has en tered the coldstart listen st ate, and will change to the integration listen state only after approximately one macrotick. mfr4200 protocol implementation document mfr4200 data sheet, rev. 0 252 freescale semiconductor moreover, in figure 7-6 (ps v1.1), and in si milar drawings for nodes b and c, the state initialize schedule lasts until the end of the communication cycle, ra ther than changing in the middle of the cycle. c.8 clock synchronization c.8.1 introduction the implementation is compliant with ps v1.1. c.8.2 time representation the implementation is compliant with ps v1.1. c.8.3 synchronization process figure 8-3 (ps v1.1): in mfr4200 the measurement ta bles are initialized during the nit (before cycle start, rather than after th e cycle start). the entries for the even cy cle are initialized in the nit of the odd cycle. likewise, the measurements of the odd cycl e are initialized in the nit of the even cycle. c.8.4 clock startup the implementation is compliant with ps v1.1. c.8.5 time measurement the implementation is compliant with ps v1.1. howeve r, note that the clock sync measurement values indicated in the host interface are different from the example shown in figure 8-8 (ps v1.1). c.8.5.1 data structure the implementation is compliant with ps v1.1. c.8.5.2 initialization in mfr4200, the table for the odd cycle me asurements is initialized in the nit of the even cycle, and vice versa, rather than after the beginning of the even cycle. c.8.6 correction term calculation figure 8-13 (ps v1.1): mfr4200 differs slightly from this description. start up frames are counted on a per channel basis, with one counter for each channel, rather than one counter for both channels. for evaluation, the maximum is taken, rather than counti ng a startup frame on either channel with a single counter. moreover, in mfr4200, the check of voffsetcorrection is performed before the external offset correction, rather th an after external offset correction. controller host interface mfr4200 data sheet, rev. 0 freescale semiconductor 253 figure 8-14 (ps v1.1): in mfr4200 the check of vratecorrection is performed before the external offset correction rather than afte r external rate correction. c.8.7 clock correction figure 8-15 (ps v1.1): the implementation in mfr4200 is compliant with the red text in the middle of the diagram. moreover, when macrotick counti ng is reset, the host interface indication of vmacrotick is immediately reset to 0, as soon as the macrotick count ing is reset; however, internally, the macrotick generation continues for a short time in accordance with the specification. c.8.8 sync frame configuration rules table 8-3 (ps v1.1): mfr4200 supports up to 16 sync frames, rather than 15. c.9 controller host interface the implementation of the host interface is comp liant with the specification in ps v1.1. the implementation supports the following features: message filtering ? frame id filtering ? cycle counter filtering ? channel filtering ? message id filtering (fifo only) message fifo (receive fifo) timer error signalling host interrupts ? timer interrupt ? error signaling interrupt network management vector c.10 device specific power modes mfr4200 supports supervision of voltage levels, a nd performs a reset when the supply voltage drops below a boundary specified in chapter 5, ?clocks and reset generator . a low power mode or sleep mode is not supported. c.11 bus guardian schedule monitoring the implementation is compliant with ps v1.1. mfr4200 protocol implementation document mfr4200 data sheet, rev. 0 254 freescale semiconductor c.12 system parameters and configuration constraints c.12.1 system parameters system parameters are used primarily for the prot ocol description and are not protocol mechanisms. therefore, they are almost transparent to the us er in the mfr4200 implemen tation. the only difference from ps v1.1 that is relevant to the user is as follows. csyncnodemax is fixed at 16. note parameters relating to unsupported f eatures are not mentioned here. c.12.2 configuration constraints the implementation requires most of the constraints specified in ps v1.1 to be fulfilled. exceptions are bit rate configuration and bit sam ple clock frequency, which are conf igurable in a wider range than described in ps v1.1. note however, while fulfilling these configur ation constraints is necessary, it is not sufficient for a valid configuration. mfr4200 data sheet, rev. 0 freescale semiconductor 255 appendix d index of registers a active fifo buffer cycle counter and payload length regi ster (afbccplr) 132 active fifo buffer data n register (afbdatanr) 133 active fifo buffer frame id register (afbfrid) 131 active fifo buffer header crc register (afbcrcr) 132 active fifo buffer message buffer slot status vector regi ster (afbmbssvr) 133 active receive buffer cycle counter a nd payload lenth regi ster (arbccplr) 129 active receive buffer data n register (arbdatanr) 130 active receive buffer frame id register (arbfrid) 129 active receive buffer header crc register (arbcrcr) 130 active receive buffer message buffer slot status vector regi ster (arbmbssvr) 131 active transmit buffer cycl e counter and payload lengt h register (atbccplr) 127 active transmit buffer data n register (atbdatanr) 128 active transmit buffer fram e id register (atbfrid) 126 active transmit buffer header crc register (atbcrcr) 127 active transmit buffer message buffer slot status vector regi ster (atbmbssvr) 128 b bit duration register (bdr) 71 buffer control, configuration a nd status n register (bufcsnr) 126 bus guardian status register (bgsr) 99 bus guardian tick register (bgtr) 87 c channel status error counter n register (csecnr) 102 chi error register (chier) 109 clock correction failed c ounter register (ccfcr) 113 cluster drift damping register (cddr) 73 cold start maximum register (csmr) 84 current cycle counter value register (cccvr) 94 current macrotick counter value register (cmcvr) 94 cycle counter filter n register (ccfnr) 135 cycle length register (clr) 80 d debug port control register (dbpcr) 88 delay compensation channel a register (dcar) 72 index of registers mfr4200 data sheet, rev. 0 256 freescale semiconductor delay compensation channe l b register (dcbr) 72 delay counter register (dcr) 87 e error handling level register (ehlr) 113 even measurement channel a n register (emanr) 122 even measurement channel b n register (embnr) 123 even measurement counter register (emcr) 124 even sync frame id n register (esfidnr) 121 external correction control register (eccr) 82 external offset correc tion register (eocr) 81 external rate correction register (ercr) 82 f fifo acceptance filter message id mask register (fafmidmr) 136 fifo acceptance filter message id value register (fafmidvr) 136 fifo acceptance/rejection filter channel register (fafchr) 137 fifo rejection filter frame id mask register (frffidmr) 138 fifo rejection filter frame id value register (frffidvr) 138 fifo size register (fsizr) 125 g global network management vect or n register (gnmvnr) 96 h host interface and physical layer pins drive strength register (hipdsr) 67 host interface pins pullup/down control register (hippcr) 69 host interface pins pullup/down enable register (hipper) 68 i idle detection length register (idlr) 90 interrupt enable register 0 (ier0) 103 interrupt status register 0 (isr0) 114 l latest dynamic transmission start register (ldtsr) 78 listen timeout with noise length register (lnlr) 92 mfr4200 data sheet, rev. 0 freescale semiconductor 257 m magic number register (mnr) 63 maximum cycle length deviation register (mcldar) 81 maximum odd cycles without clock co rrection fatal register (mocwcfr) 101 maximum odd cycles without clock corr ection passive register (mocwcpr) 101 maximum offset correction register (mocr) 83 maximum payload length dyna mic register (mpldr) 79 maximum rate correction register (mrcr) 84 maximum sync frames register (msfr) 73 microticks per cycle hi gh register (mpchr) 75 microticks per cycle low register (mpclr) 74 minislot action point offs et register (msapor) 77 minislot length register (mslr) 77 module configuration register 0 (mcr0) 64 module configuration register 1 (mcr1) 66 module version register 0 (mvr0) 62 module version register 1 (mvr1) 62 n network idle time configur ation register (nitcr) 80 network management vector length register (nmvlr) 85 nominal macrotick lengt h register (nmlr) 74 number of static slots register (nssr) 76 o odd measurement channel a n register (omanr) 121 odd measurement channel b n register (ombnr) 122 odd measurement counter register (omcr) 124 odd sync frame id n register (osfidnr) 120 offset correction value register (ocvr) 95 p physical layer pins drive st rength register (plpdsr) 68 physical layer pins pullup/dow n control register (plppcr) 70 physical layer pins pullup/dow n enable register (plpper) 69 protocol state register (psr) 93 r rate correction value register (rcvr) 95 receive buffer interrupt v ector register (rbivecr) 108 index of registers mfr4200 data sheet, rev. 0 258 freescale semiconductor s slot status counter conditi on n register (ssccnr) 105 slot status counter increm entation register (sscir) 107 slot status counter interrupt mask register (sscimr) 107 slot status counter n register (sscnr) 104 slot status n regi ster (ssnr) 119 slot status selection n register (sssnr) 103 start of offset correction cycl e time register (socctr) 89 startup interrupt enable register (sier) 100 startup interrupt status register (sisr) 118 static payload length register (splr) 76 static slot action point of fset register (ssapor) 78 static slot length register (sslr) 75 symbol window configuration register (swcr) 79 symbol window control register (swctrlr) 90 symbol window status channel a register (swsar) 97 symbol window status channel b register (swsbr) 98 sync frame acceptance filter mask register (synfafmr) 134 sync frame acceptance filter value register (synfafvr) 134 sync frame header register (synchr) 86 sync frame register (syncfr) 86 sync frame rejection filt er register (synfrfr) 135 t timer interrupt configuration re gister 0 cycle set (ticr0cs) 139 timer interrupt configuration regist er 0 macrotick o ffset (ticr0mo) 140 timer interrupt configuration re gister 1 cycle set (ticr1cs) 140 timer interrupt configuration regist er 1 macrotick o ffset (ticr1mo) 141 transmit buffer interrupt v ector register (tbivecr) 109 transmit start sequence length register (tsslr) 85 v voltage regulator status register (vregsr) 70 w wakeup mechanism control register (wmctrlr) 91 wakeup symbol tx idle register (wustxir) 91 wakeup symbol tx low register (wustxlr) 92 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2004. all rights reserved. mfr4200 rev. 0 8/2005 |
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